Generel Characteristics: |
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Designer | ARM |
Type: | Cortex-A9 MPCore |
Year Released: | 2009 |
Function | Multi-core Application Processor |
Architecture: |
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Width of Machine Word | 32 bit |
Supported Instruction Set(s): | ARMv7-A |
Pipeline Stages | 8 pipeline stages |
Type of processor core(s) | 2x ARM Cortex-A9 MPcore |
Number of processor core(s): | dual-core |
Buses: |
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Memory Interface(s): | Yes |
Data Bus Width | 64 bit |
Number of data bus channels: | 1 ch |
Non-volatile Memory Interface | No |
Clock Frequencies: |
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Recommended Maximum Clock Frequency: | N/A |
Cache Memories: |
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Technology and Packaging: |
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Semiconductor Technology: | CMOS |
Graphical Subsystem: |
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Embedded GPU | N/A |
Cellular Communication: |
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Supported Cellular Data Links | No |
Additional Information: |
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Special Features: 2x Cortex-A9 Harvard Superscalar processor, Configurable L1 and L2 cache sizes, FPU, MMU, 64 bit AMBA 3.0 AXI bus, NEON Media Processing technology, ARM Thumb-2 Technology, ARM TrustZone Technology, ARM CoreSight, ARM Jazelle RCT + DBX |
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Datasheet Attributes: |
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Data Integrity | Final |
Added | 2009-07-18 14:01 |
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