Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
ARM |
Type: |
Cortex-A15 MPcore |
Codename: |
Eagle |
Year Released: |
2010 |
Function |
Multi-core Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7-A |
Number of processor core(s): |
4 |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
4x ARM Cortex-A15 MPcore |
Buses:
|
Memory Interface(s): |
Yes |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
128 bit |
Number of data bus channels: |
1 ch |
Non-volatile Memory Interface |
No |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
2500 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte D-Cache |
Technology and Packaging:
|
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
N/A |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Communication Interfaces:
|
Supported USB Specification: |
No |
Bluetooth support |
No |
Wireless LAN support |
No |
Supported Audio/Video Interface: |
No |
Satellite Navigation:
|
Supported GPS protocol(s): |
No |
Additional Information:
|
Special Features: up to 4x Cortex-A15 Harvard Superscalar processor core, Configurable per processor L1 (up to 32KB+32KB) and common L2 (up to 4MB) cache sizes, VFPv4 FPU, MMU, 128bit AMBA 4 Advanced Coherent Bus, Snopp Control Unit, NEON Media Processing technology, ARM Thumb-2 Technology, ARM TrustZone Technology, ARM CoreSight, ARM Jazelle RCT + DBX, ARM CoreSight Multi-core debug and trace function |
Datasheet Attributes:
|
Related Page: |
URL |
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2010-09-19 20:15 |