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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component ARM
Type Cortex-A7 MPCore
Year Released 2012
FunctionMain function of the component  Multi-core Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv7-A
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 8 pipeline stages
Type of processor core(s)Type and allocation of processor core(s) 2x ARM Cortex-A7 MPcore
Number of processor core(s) dual-core

BusesBuses: 
Memory Interface(s):   Yes
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 64 bit
Number of data bus channels 1 ch
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  No


Clock FrequenciesClock Frequencies: 
Recommended Minimum Clock Frequency 1000 MHz min.
Recommended Maximum Clock Frequency N/A

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 32 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 32 Kbyte D-Cache

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 28 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Additional InformationAdditional Information: 
Special Features
2x Cortex-A7 Harvard Superscalar processor, 8-stage pipeline, configurable cache sizes (8 - 64 Kbyte), VFPv4, ARMv7 MMU, 64 bit AMBA AXI bus, NEON Media Processing technology, ARM Thumb-2 Technology, ARM TrustZone Technology, ARM CoreSight, ARM Jazelle RCT + DBX

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2013-06-03 22:05
 
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