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Designer![]() |
ARM |
Type: | Cortex-A7 MPCore |
Year Released: | 2012 |
Function![]() |
Multi-core Application Processor |
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Width of Machine Word![]() |
32 bit |
Supported Instruction Set(s): | ARMv7-A |
Pipeline Stages![]() |
8 pipeline stages |
Type of processor core(s)![]() |
2x ARM Cortex-A7 MPcore |
Number of processor core(s): | dual-core |
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Memory Interface(s): | Yes |
Data Bus Width![]() |
64 bit |
Number of data bus channels: | 1 ch |
Non-volatile Memory Interface![]() |
No |
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Recommended Minimum Clock Frequency: | 1000 MHz min. |
Recommended Maximum Clock Frequency: | N/A |
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L1 Instruction Cache per Core![]() |
32 Kbyte I-Cache |
L1 Data Cache per Core![]() |
32 Kbyte D-Cache |
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Feature Size![]() |
28 nm |
Semiconductor Technology: |
CMOS![]() |
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Embedded GPU![]() |
N/A |
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Supported Cellular Data Links![]() |
No |
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Supported GPS protocol(s): | No |
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Special Features: | 2x Cortex-A7 Harvard Superscalar processor, 8-stage pipeline, configurable.. ›› |
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Data Integrity![]() |
Final |
Added![]() |
2013-06-03 22:05 |
Tweet | |