Generel Characteristics:
|
Designer |
ARM |
Type: |
Cortex-A7 MPCore |
Year Released: |
2012 |
Function |
Multi-core Application Processor |
Architecture:
|
Width of Machine Word |
32 bit |
Supported Instruction Set(s): |
ARMv7-A |
Pipeline Stages |
8 pipeline stages |
Number of processor core(s): |
2 |
Type of processor core(s) |
2x ARM Cortex-A7 MPcore |
Buses:
|
Memory Interface(s): |
Yes |
Data Bus Width |
64 bit |
Number of data bus channels: |
1 ch |
Non-volatile Memory Interface |
No |
Clock Frequencies:
|
Recommended Minimum Clock Frequency: |
1000 MHz min. |
Recommended Maximum Clock Frequency: |
N/A |
Cache Memories:
|
L1 Instruction Cache per Core |
32 Kbyte I-Cache |
L1 Data Cache per Core |
32 Kbyte D-Cache |
Technology and Packaging:
|
Feature Size |
28 nm |
Semiconductor Technology: |
CMOS |
Graphical Subsystem:
|
Embedded GPU |
N/A |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Communication Interfaces:
|
Supported USB Specification: |
No |
Bluetooth support |
No |
Wireless LAN support |
No |
Supported Audio/Video Interface: |
No |
Satellite Navigation:
|
Supported GPS protocol(s): |
No |
Additional Information:
|
Special Features: 2x Cortex-A7 Harvard Superscalar processor, 8-stage pipeline, configurable cache sizes (8 - 64 Kbyte), VFPv4, ARMv7 MMU, 64 bit AMBA AXI bus, NEON Media Processing technology, ARM Thumb-2 Technology, ARM TrustZone Technology, ARM CoreSight, ARM Jazelle RCT + DBX |
Datasheet Attributes:
|
Related Page: |
URL |
Data Integrity |
Final |
Added |
2013-06-03 22:05 |