Generel Characteristics: |
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Designer | ARM |
Type: | Cortex-A8 |
Year Released: | 2005 |
Function | Application Processor |
Architecture: |
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Width of Machine Word | 32 bit |
Supported Instruction Set(s): | ARMv7-A |
Pipeline Stages | 13 pipeline stages |
Number of processor core(s): | 1 |
Type of processor core(s) | ARM Cortex |
Buses: |
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Memory Interface(s): | Yes |
Data Bus Width | 32 bit |
Number of data bus channels: | 1 ch |
Non-volatile Memory Interface | No |
Clock Frequencies: |
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Recommended Maximum Clock Frequency: | N/A |
Cache Memories: |
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L1 Instruction Cache per Core | 32 Kbyte I-Cache |
L1 Data Cache per Core | 32 Kbyte D-Cache |
Total L2 Cache | 1024 Kbyte L2 |
Technology and Packaging: |
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Feature Size | 65 nm |
Semiconductor Technology: | CMOS |
Graphical Subsystem: |
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Embedded GPU | N/A |
Cellular Communication: |
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Supported Cellular Data Links | No |
Communication Interfaces: |
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Supported USB Specification: | No |
Bluetooth support | No |
Wireless LAN support | No |
Supported Audio/Video Interface: | No |
Satellite Navigation: |
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Supported GPS protocol(s): | No |
Additional Information: |
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Instruction Execution Performance: | 2000 million instruction per |
Instruction Execution Performance Clock Rate: | 1000 MHz |
Special Features: Superscalar processor, Configurable L1 and L2 cache sizes, FPU, MMU, AMBA 3.0 AXI bus, NEON Media Processing technology, ARM Thumb-2 Technology, ARM TrustZone Technology, ARM CoreSight, ARM Jazelle RCT |
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Datasheet Attributes: |
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Related Page: | URL |
Data Integrity | Final |
Added | 2007-09-04 17:10 |
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