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Designer![]() |
Apple |
Type: | A11 Bionic APL1072 / APL1W72 |
Codename: | T8015 |
Year Released: | 2017 |
Function![]() |
SoC |
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Width of Machine Word![]() |
64 bit |
Supported Instruction Set(s): | ARMv8.2-A |
Type of processor core(s)![]() |
2x Apple Monsoon + 4x Apple Mistral cores |
Number of processor core(s): | hexa-core |
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Memory Interface(s): | LPDDR4 SDRAM , LPDDR4x SDRAM |
Max. Clock Frequency of Memory IF![]() |
2064 MHz |
Data Bus Width![]() |
16 bit |
Number of data bus channels: | 4 ch |
Max. Data Rate![]() |
33.02 Gbyte/s |
Non-volatile Memory Interface![]() |
eMMC 5.1![]() ![]() ![]() |
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Recommended Maximum Clock Frequency: | 2376 MHz max. |
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L1 Instruction Cache per Core![]() |
64 Kbyte I-Cache |
L1 Data Cache per Core![]() |
64 Kbyte D-Cache |
Total L2 Cache![]() |
8192 Kbyte L2 |
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Feature Size![]() |
10 nm |
Semiconductor Technology: |
FinFET![]() |
Number of Transistors Integrated: | 4300000000 |
Fab![]() |
TSMC |
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Embedded GPU![]() |
Apple A11 GPU |
Number of GPU cores: | 3-core GPU |
GPU Clock: | 1066 MHz GPU |
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Supported Cellular Data Links![]() |
No |
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Special Features: TMHS09, 2x high-performance 2.38 GHz Apple Monsoon 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (64 Kbyte L1i cache per core + 64 Kbyte L1d cache per core) + 4x high-efficiency 1.19 GHz Apple Mistral 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar.. ›› |
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Data Integrity![]() |
Preliminary |
Added![]() |
2017-09-12 23:54 |
Tweet | |