Generel Characteristics: |
|
Designer | Apple |
Type: | A11 Bionic APL1072 / APL1W72 |
Codename: | T8015 |
Year Released: | 2017 |
Function | SoC |
Architecture: |
|
Width of Machine Word | 64 bit |
Supported Instruction Set(s): | ARMv8.2-A |
Type of processor core(s) | 2x Apple Monsoon + 4x Apple Mistral cores |
Number of processor core(s): | hexa-core |
Buses: |
|
Memory Interface(s): | LPDDR4 SDRAM , LPDDR4x SDRAM |
Max. Clock Frequency of Memory IF | 2064 MHz |
Data Bus Width | 16 bit |
Number of data bus channels: | 4 ch |
Max. Data Rate | 33.02 Gbyte/s |
Non-volatile Memory Interface | eMMC 5.1 , moviNAND , NAND Flash Interface , SATA |
Clock Frequencies: |
|
Recommended Maximum Clock Frequency: | 2376 MHz max. |
Cache Memories: |
|
L1 Instruction Cache per Core | 64 Kbyte I-Cache |
L1 Data Cache per Core | 64 Kbyte D-Cache |
Total L2 Cache | 8192 Kbyte L2 |
Technology and Packaging: |
|
Feature Size | 10 nm |
Semiconductor Technology: | FinFET |
Number of Transistors Integrated: | 4300000000 |
Fab | TSMC |
Graphical Subsystem: |
|
Embedded GPU | Apple A11 GPU |
Number of GPU cores: | 3-core GPU |
GPU Clock: | 1066 MHz GPU |
Cellular Communication: |
|
Supported Cellular Data Links | No |
Additional Information: |
|
Special Features: TMHS09, 2x high-performance 2.38 GHz Apple Monsoon 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (64 Kbyte L1i cache per core + 64 Kbyte L1d cache per core) + 4x high-efficiency 1.19 GHz Apple Mistral 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar.. ›› |
|
Datasheet Attributes: |
|
Data Integrity | Preliminary |
Added | 2017-09-12 23:54 |
Tweet | |