Generel Characteristics: |
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Designer | Apple |
Type: | A10 Fusion APL1024 / APL1W24 |
Codename: | T8010 |
Year Released: | 2016 |
Function | SoC |
Architecture: |
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Width of Machine Word | 64 bit |
Supported Instruction Set(s): | ARMv8.1-A (A32, A64) |
Type of processor core(s) | 2x Apple Hurricane + 2x Apple Zephyr cores |
Number of processor core(s): | quad-core |
Buses: |
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Memory Interface(s): | LPDDR4 SDRAM |
Max. Clock Frequency of Memory IF | 1600 MHz |
Data Bus Width | 64 bit |
Number of data bus channels: | 1 ch |
Max. Data Rate | 25.6 Gbyte/s |
Non-volatile Memory Interface | eMMC 5.1 , moviNAND , NAND Flash Interface , SATA |
Clock Frequencies: |
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Recommended Minimum Clock Frequency: | 396 MHz min. |
Recommended Maximum Clock Frequency: | 2370 MHz max. |
Cache Memories: |
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L1 Instruction Cache per Core | 64 Kbyte I-Cache |
L1 Data Cache per Core | 64 Kbyte D-Cache |
Total L2 Cache | 3072 Kbyte L2 |
Total L3 Cache: | 4096 Kbyte L3 |
Technology and Packaging: |
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Feature Size | 16 nm |
Semiconductor Technology: | FinFET |
Number of Transistors Integrated: | 3300000000 |
Fab | TSMC |
Graphical Subsystem: |
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Embedded GPU | IMG PowerVR GT7600 Plus GPU |
Number of GPU cores: | 6-core GPU |
GPU Clock: | 900 MHz GPU |
Cellular Communication: |
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Supported Cellular Data Links | No |
Additional Information: |
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Special Features: 2x high-performance 2.37 GHz Apple Hurricane 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (64 Kbyte L1i cache per core + 64 Kbyte L1d cache per core) + 2x high-efficiency 1.68 GHz Apple Zephyr 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores.. ›› |
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Datasheet Attributes: |
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Data Integrity | Preliminary |
Added | 2016-08-12 14:04 |
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