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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Ingenic
Type Jz4755
Year Released 2009
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) MIPS32
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 8 pipeline stages
Type of processor core(s)Type and allocation of processor core(s) MIPS XBurst
Number of processor core(s) single-core

BusesBuses: 
Memory Interface(s):   SDRAM
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Non-volatile Memory Data Bus WidthMaximum selectable bit width of secondary data (non-volatile storage) bus of memory interface 32 bit
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  NAND Flash Interface


Clock FrequenciesClock Frequencies: 
Recommended Minimum Clock Frequency 360 MHz min.
Recommended Maximum Clock Frequency 400 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 16 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 16 Kbyte D-Cache

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 160 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
PinsNumber of pins on the package 176 pins

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A

Cellular CommunicationCellular Communication: 

Supported Cellular Data LinksList of supported cellular data links  No

Satellite NavigationSatellite Navigation: 

Supported GPS protocol(s):   No

Additional InformationAdditional Information: 
Special Features dual core CPU, XBurst 8-stage pipeline micro-architecture, XBurst.. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2009-11-07 00:31
 
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