 Generel Characteristics:
|
Designer |
Ingenic |
| Type: |
Jz4755 |
| Year Released: |
2009 |
| Function |
Application Processor |
 Architecture:
|
| Width of Machine Word |
32 bit |
| Supported Instruction Set(s): |
MIPS32 |
| Pipeline Stages |
8 pipeline stages |
| Type of processor core(s) |
MIPS XBurst |
| Number of processor core(s): |
single-core |
 Buses:
|
| Memory Interface(s): |
SDRAM |
| Data Bus Width |
32 bit |
| Number of data bus channels: |
1 ch |
| Non-volatile Memory Data Bus Width |
32 bit |
| Non-volatile Memory Interface |
NAND Flash Interface |
 Clock Frequencies:
|
| Recommended Minimum Clock Frequency: |
360 MHz min. |
| Recommended Maximum Clock Frequency: |
400 MHz max. |
 Cache Memories:
|
| L1 Instruction Cache per Core |
16 Kbyte I-Cache |
| L1 Data Cache per Core |
16 Kbyte D-Cache |
 Technology and Packaging:
|
| Feature Size |
160 nm |
| Semiconductor Technology: |
CMOS |
| Pins |
176 pins |
 Graphical Subsystem:
|
| Embedded GPU |
N/A |
 Cellular Communication:
|
| Supported Cellular Data Links |
No |
 Additional Information:
|
Special Features:
dual core CPU, XBurst 8-stage pipeline micro-architecture, XBurst SIMD instruction set to support multimedia acceleration, XBurst CPU for video processing, SDRAM controller, 8 ch. DMC, Multimedia accelerator, LCD Controller, MMC/SD/SDIO controller, camera interface, 802.3 compliant Ethernet interface |
 Datasheet Attributes:
|
| Data Integrity |
Preliminary |
| Added |
2009-11-07 00:31 |
All details | 
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