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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Ingenic
Type M200
Year Released 2015
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) MIPS32
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 9 pipeline stages
Number of processor core(s) 2
Type of processor core(s)Type and allocation of processor core(s) 1x MIPS XBurst-HP + 1x MIPS XBurst-LP

BusesBuses: 
Memory Interface(s):   mobile (LP) DDR SDRAM , DDR2 SDRAM , mobile (LP) DDR2 SDRAM , DDR3 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 667 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 5.34 Gbyte/s
Non-volatile Memory Data Bus WidthMaximum selectable bit width of secondary data (non-volatile storage) bus of memory interface 64 bit
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  NAND Flash Interface
DMA ChannelsDMA (Direct Memory Access) allows direct data transfer between operative memory (RAM) and peripherals (hard disk, non-volatile storage, etc.) bypassing processor core. Multiple DMA channels allows parallel DMA operations. 32 ch


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 1200 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 32 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 32 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 512 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
PinsNumber of pins on the package 270 pins

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A
Number of GPU cores 1-core GPU

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Communication InterfacesCommunication Interfaces: 
Supported USB Specification:   No
Bluetooth supportThis field specifies the supported BT version  No
Wireless LAN supportThis field enumerates the supported Wi-Fi protocols  No
Supported Audio/Video Interface:   No

Satellite NavigationSatellite Navigation: 
Supported GPS protocol(s):   No

Additional InformationAdditional Information: 
Special Features
1x XBurst-HP (1.2GHz) + 1x XBurst-LP (300 MHz) cores, SIMD instruction set, 16/32-bit SD RAM interface, 64-bit ECC NAND flash support, 512B/2KB/4KB/8KB/16KB page size, Xburst VPU, OpenGL ES2.0 and ES1.1, OpenVG1.1, 720p 30 fps video encode, 720p 30 fps video decode, AC97/I2S/SPDIF, Audio Codec, LCD interface, ISP, USB 2.0 OTG.

Datasheet AttributesDatasheet Attributes: 

Related Page URL
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2018-02-09 15:37
 
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