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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Ingenic
Type Jz4770
Year Released 2011
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) MIPS32
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 8 pipeline stages
Number of processor core(s) 1
Type of processor core(s)Type and allocation of processor core(s) MIPS XBurst

BusesBuses: 
Memory Interface(s):   mobile (LP) DDR SDRAM
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  NAND Flash Interface , NOR Flash Interface
DMA ChannelsDMA (Direct Memory Access) allows direct data transfer between operative memory (RAM) and peripherals (hard disk, non-volatile storage, etc.) bypassing processor core. Multiple DMA channels allows parallel DMA operations. 12 ch


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 1000 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 16 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 16 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 256 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 65 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
PinsNumber of pins on the package 379 pins
Supply Voltage 1.2 V

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). Vivante GC860 GPU
GPU Clock 444 MHz GPU

Cellular CommunicationCellular Communication: 

Supported Cellular Data LinksList of supported cellular data links  No

Satellite NavigationSatellite Navigation: 

Supported GPS protocol(s):   No

Additional InformationAdditional Information: 
Special Features XBurst SIMD instruction set, 8-stage pipeline, 16/32-bit LP-DDR/DDR/DDR2 SD RAM interface, 8/16-bit SRAM interface, NOR Flash SLC/MLC/TLC NAND Flash interface, 4/8/12/16/20/24 bit ECC, SRAM interface, 12-ch DMA, 500MHz Xburst VPU, 1080p HD video decode, 444MHz Vivante GC860 GPU, OpenGL ES2.0 and ES1.0, OpenVG1.1, AC97/I2S/SPDIF, Audio Codec, LCD interface, LVDS, TV Encoder, EPD interface, 16.7MP camera interface, Touch ADC, 1-wire, PCM, I2C, SPI, UART, SIM-IF, SD/MMC/SDIO, USB Host, USB OTG 2.0, TS-IF, GPIO, Ethernet MAC, OTP Slave

Datasheet AttributesDatasheet Attributes: 

Related Page URL
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2011-12-13 15:05
 
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