Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
MediaTek |
Type: |
Dimensity 8100-Ultra MT6895ZB |
Year Released: |
2022 |
Function |
Multi-core Application Processor with Modem |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
64 bit |
Supported Instruction Set(s): |
ARMv8.2-A |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
4x ARM Cortex-A78 + 4x ARM Cortex-A55 MPcore |
Number of processor core(s): |
octa-core |
Buses:
|
Memory Interface(s): |
LPDDR4x SDRAM
, LPDDR5 SDRAM |
Max. Clock Frequency of Memory IF![Clock frequency of fastest supported memory interface Clock frequency of fastest supported memory interface](icons/10x10/info_gray.gif) |
3200 MHz |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
16 bit |
Number of data bus channels: |
4 ch |
Max. Data Rate![Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units.](icons/10x10/info_gray.gif) |
51.2 Gbyte/s |
Non-volatile Memory Interface |
UFS 3.1
, UFS 3.1 2-lane![Complies with dual-lane Universal Flash Storage 3.1 revision offering 2.9 GB/s NAND flash data rate Complies with dual-lane Universal Flash Storage 3.1 revision offering 2.9 GB/s NAND flash data rate](icons/10x10/info_gray.gif) |
Clock Frequencies:
|
Recommended Minimum Clock Frequency: |
200 MHz min. |
Recommended Maximum Clock Frequency: |
2849 MHz max. |
Cache Memories:
|
Total L3 Cache: |
4096 Kbyte L3 |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
5 nm |
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Fab![Plant which fabricates the semiconductor component Plant which fabricates the semiconductor component](icons/10x10/info_gray.gif) |
TSMC |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
ARM Mali-G610 GPU |
Number of GPU cores: |
6-core GPU |
Cellular Communication:
|
Supported Cellular Data Links |
CSD
, GPRS
, EDGE
, UMTS
, HSUPA
, HSUPA 1.4
, HSUPA 2.0
, HSUPA 5.8
, HSUPA 11.5
, HSDPA
, HSDPA 1.8
, HSDPA 3.6
, HSDPA 7.2
, HSDPA 10.2
, HSDPA 14.4
, HSPA+ 21.1
, HSPA+ 42.2
, DC-HSDPA 42.2
, CDMA2000 1x
, CDMA2000 1xEV-DO
, CDMA2000 1xEV-DO Rev A
, TD-SCDMA
, LTE
, LTE 100/50
, LTE 150/50
, LTE 300/50
, LTE 300/100
, LTE 400/150
, LTE 600/100
, LTE 1600
, NR 2600
, NR 3700
, NR 4600 data links |
Additional Information:
|
Special Features: MT6895Z/B_TCZA, 4x ARM Cortex-A78 (up to 2.85 GHz) + 4x ARM Cortex-A55 (up to 2.05 GHz) Harvard Superscalar processor core, HMP, integrated GSM / GPRS / UMTS / DC-HSPA / HSUPA / TD-SCDMA 2.8 Mbps / CDMA2000 1xRTT EV-DO Rev... ›› |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2023-03-09 09:57 |