Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
MediaTek |
Type: |
Dimensity 7030 MT6879 |
Year Released: |
2023 |
Function |
Multi-core Application Processor with Modem |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
64 bit |
Supported Instruction Set(s): |
ARMv8.2-A |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
2x ARM Cortex-A78 + 6x ARM Cortex-A55 MPcore |
Number of processor core(s): |
octa-core |
Buses:
|
Memory Interface(s): |
LPDDR4x SDRAM
, LPDDR5 SDRAM |
Max. Clock Frequency of Memory IF![Clock frequency of fastest supported memory interface Clock frequency of fastest supported memory interface](icons/10x10/info_gray.gif) |
3200 MHz |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
16 bit |
Number of data bus channels: |
4 ch |
Max. Data Rate![Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units.](icons/10x10/info_gray.gif) |
51.2 Gbyte/s |
Non-volatile Memory Interface |
UFS 2.1
, UFS 3.1![UFS 3.1 (released as JESD220E in 2020) defines single-lane 1.45 GB/s or dual-lane 2.9 GB/s NAND flash EEPROM interface UFS 3.1 (released as JESD220E in 2020) defines single-lane 1.45 GB/s or dual-lane 2.9 GB/s NAND flash EEPROM interface](icons/10x10/info_gray.gif) |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
2500 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
64 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
64 Kbyte D-Cache |
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
1280 Kbyte L2 |
Total L3 Cache: |
2048 Kbyte L3 |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
6 nm |
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Fab![Plant which fabricates the semiconductor component Plant which fabricates the semiconductor component](icons/10x10/info_gray.gif) |
TSMC |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
ARM Mali-G610 GPU |
Number of GPU cores: |
3-core GPU |
GPU Clock: |
1000 MHz GPU |
Cellular Communication:
|
Supported Cellular Data Links |
CSD
, GPRS
, EDGE
, UMTS
, HSUPA
, HSUPA 1.4
, HSUPA 2.0
, HSUPA 5.8
, HSUPA 11.5
, HSDPA
, HSDPA 1.8
, HSDPA 3.6
, HSDPA 7.2
, HSDPA 10.2
, HSDPA 14.4
, HSPA+ 21.1
, HSPA+ 42.2
, DC-HSDPA 42.2
, CDMA2000 1x
, CDMA2000 1xEV-DO
, CDMA2000 1xEV-DO Rev A
, TD-SCDMA
, LTE
, LTE 100/50
, LTE 150/50
, LTE 300/50
, LTE 300/100
, LTE 400/150
, LTE 600/100
, LTE 1000/100
, LTE 1200/200
, LTE 1600
, NR 2600
, NR 3700
, NR 4600 data links |
Additional Information:
|
Special Features: 2x ARM Cortex-A78 (up to 2.5 GHz, 128 Kbyte L1 cache per core, 256 Kbyte L2 cache per core) + 6x ARM Cortex-A55 (up to 2 GHz, 64 Kbyte L1 cache per core, 128 Kbyte L2 cache per core) Harvard.. ›› |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2024-05-14 21:16 |