Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Apple |
Type: |
A9 APL1022 |
Codename: |
S8003 |
Year Released: |
2015 |
Function |
Multi-core Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
64 bit |
Supported Instruction Set(s): |
ARMv8-A (A32, A64) |
Pipeline Stages![Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions.](icons/10x10/info_gray.gif) |
16 pipeline stages |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
2x Apple Twister cores |
Number of processor core(s): |
dual-core |
Buses:
|
Memory Interface(s): |
LPDDR4 SDRAM |
Max. Clock Frequency of Memory IF![Clock frequency of fastest supported memory interface Clock frequency of fastest supported memory interface](icons/10x10/info_gray.gif) |
1600 MHz |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
64 bit |
Number of data bus channels: |
1 ch |
Max. Data Rate![Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units.](icons/10x10/info_gray.gif) |
25.6 Gbyte/s |
Non-volatile Memory Interface |
eMMC 5.0
, moviNAND
, NAND Flash Interface
, SATA![SATA revision 1.0 (2003) offering 1.5 Gbit/s data rate SATA revision 1.0 (2003) offering 1.5 Gbit/s data rate](icons/10x10/info_gray.gif) |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
1840 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
64 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
64 Kbyte D-Cache |
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
3072 Kbyte L2 |
Total L3 Cache: |
4096 Kbyte L3 |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
16 nm |
Semiconductor Technology: |
FinFET![Multigate (usually double-gate) MOSFET transistor technology Multigate (usually double-gate) MOSFET transistor technology](icons/10x10/info_gray.gif) |
Fab![Plant which fabricates the semiconductor component Plant which fabricates the semiconductor component](icons/10x10/info_gray.gif) |
TSMC |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
IMG PowerVR GT7600 GPU |
Number of GPU cores: |
6-core GPU |
GPU Clock: |
650 MHz GPU |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Additional Information:
|
Special Features: 2x Custom Apple Twister 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores, HMP, ARM VFPv4, 4 Mbyte (victim) L3 cache, 2160p video encode, 2160p video decode, OpenCL 1.2, OpenGL, Vulkan, DirectX 11 |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2016-09-15 12:35 |