Generel Characteristics: |
|
Designer | NVIDIA |
Type: | Tegra 3 T33 |
Codename: | Kal-El |
Year Released: | 2012 |
Function | Multi-core Application Processor |
Architecture: |
|
Width of Machine Word | 32 bit |
Supported Instruction Set(s): | ARMv7-A |
Pipeline Stages | 8 pipeline stages |
Type of processor core(s) | 5x ARM Cortex-A9 MPCore |
Number of processor core(s): | penta-core |
Buses: |
|
Memory Interface(s): | LPDDR2 SDRAM , DDR3L SDRAM |
Max. Clock Frequency of Memory IF | 800 MHz |
Data Bus Width | 32 bit |
Number of data bus channels: | 1 ch |
Max. Data Rate | 6.4 Gbyte/s |
Non-volatile Memory Interface | NAND Flash Interface |
Clock Frequencies: |
|
Recommended Minimum Clock Frequency: | 1600 MHz min. |
Recommended Maximum Clock Frequency: | 1700 MHz max. |
Cache Memories: |
|
L1 Instruction Cache per Core | 32 Kbyte I-Cache |
L1 Data Cache per Core | 32 Kbyte D-Cache |
Total L2 Cache | 1024 Kbyte L2 |
Technology and Packaging: |
|
Feature Size | 40 nm |
Semiconductor Technology: | CMOS |
Fab | TSMC |
Graphical Subsystem: |
|
Embedded GPU | NVIDIA GeForce ULP MP12 GPU |
Number of GPU cores: | 12-core GPU |
GPU Clock: | 520 MHz GPU |
Cellular Communication: |
|
Supported Cellular Data Links | No |
Additional Information: |
|
Special Features: 4x Cortex-A9 Harvard Superscalar primary core, 1x 500MHz Cortex-A9 Harvard Superscalar companion core, 32KB I-cache + 32KB D-cache per core, 1MB L2 cache in total, 32-bit LP-DDR2-1066 and DDR3-L-1600 SD RAM interface, ARM NEON instruction set, Enhanced NAND Flash support,.. ›› |
|
Datasheet Attributes: |
|
Data Integrity | Final |
Added | 2012-02-27 20:51 |
Tweet | |