|
|
| Designer |
NVIDIA |
| Type: | Tegra 3 AP30H |
| Codename: | Kal-El |
| Year Released: | 2011 |
| Function |
Multi-core Application Processor |
|
|
| Width of Machine Word |
32 bit |
| Supported Instruction Set(s): | ARMv7-A |
| Pipeline Stages |
8 pipeline stages |
| Type of processor core(s) |
5x ARM Cortex-A9 MPCore |
| Number of processor core(s): | penta-core |
|
|
| Memory Interface(s): | LPDDR2 SDRAM , DDR3L SDRAM |
| Max. Clock Frequency of Memory IF |
750 MHz |
| Data Bus Width |
32 bit |
| Number of data bus channels: | 1 ch |
| Max. Data Rate |
6 Gbyte/s |
| Non-volatile Memory Interface |
NAND Flash Interface |
|
|
| Recommended Maximum Clock Frequency: | 1600 MHz max. |
|
|
| L1 Instruction Cache per Core |
32 Kbyte I-Cache |
| L1 Data Cache per Core |
32 Kbyte D-Cache |
| Total L2 Cache |
1024 Kbyte L2 |
|
|
| Feature Size |
40 nm |
| Semiconductor Technology: |
CMOS |
| Fab |
TSMC |
|
|
| Embedded GPU |
NVIDIA GeForce ULP MP12 GPU |
| Number of GPU cores: | 12-core GPU |
|
|
| Supported Cellular Data Links |
No |
|
|
| Special Features: 4x Cortex-A9 Harvard Superscalar primary core, 1x 500MHz Cortex-A9 Harvard Superscalar companion core, 32KB I-cache + 32KB D-cache per core, 1MB L2 cache in total, 32-bit LP-DDR2-1066 and DDR3-L-1500 SD RAM interface, ARM NEON instruction set, Enhanced NAND Flash support,.. ›› |
|
|
|
| Data Integrity |
Preliminary |
| Added |
2011-10-08 17:30 |
| Tweet | |