Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Qualcomm |
Type: |
Snapdragon S2 MSM8655 |
Year Released: |
2011 |
Function |
Application Processor with Modem |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7 |
Pipeline Stages![Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions.](icons/10x10/info_gray.gif) |
10 pipeline stages |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
Qualcomm Scorpion |
Number of processor core(s): |
single-core |
Buses:
|
Memory Interface(s): |
LPDDR2 SDRAM |
Max. Clock Frequency of Memory IF![Clock frequency of fastest supported memory interface Clock frequency of fastest supported memory interface](icons/10x10/info_gray.gif) |
333 MHz |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
32 bit |
Number of data bus channels: |
2 ch |
Max. Data Rate![Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units.](icons/10x10/info_gray.gif) |
5.33 Gbyte/s |
Non-volatile Memory Interface |
Yes |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
1000 MHz max. |
Cache Memories:
|
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
256 Kbyte L2 |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
45 nm |
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Fab![Plant which fabricates the semiconductor component Plant which fabricates the semiconductor component](icons/10x10/info_gray.gif) |
TSMC |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
Qualcomm Adreno 205 GPU |
GPU Clock: |
266 MHz GPU |
Cellular Communication:
|
Supported Cellular Data Links |
CDMA2000 1x
, CDMA2000 1xEV-DO
, CDMA2000 1xEV-DO Rev A
, CDMA2000 1xEV-DO Rev B data links |
Additional Information:
|
Special Features: Embedded DSP (MBMS, CDMA2000 1xRTT, CDMA2000 1xEV-DO, CDMA2000 1xEV-DO Rev. 1, CDMA2000 1xEV-DO Rev. B, baseband), Embedded gpsOne Gen7 GPS module with GLONASS, gpsOneXTRA Assistance, OpenGL ES 2.0, OpenGL ES 1.1, OpenVG 1.1, EGL 1.3, Direct3D Mobile, SVGT 1.2, Direct.. ›› |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2011-01-07 09:31 |