Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Texas Instruments |
Type: |
OMAP 3620 |
Year Released: |
2009 |
Function |
Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7 |
Pipeline Stages![Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions.](icons/10x10/info_gray.gif) |
13 pipeline stages |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
ARM Cortex-A8 |
Number of processor core(s): |
single-core |
Buses:
|
Memory Interface(s): |
Yes |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
32 bit |
Number of data bus channels: |
1 ch |
Non-volatile Memory Data Bus Width![Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface](icons/10x10/info_gray.gif) |
32 bit |
Non-volatile Memory Interface |
Yes |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
720 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte D-Cache |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
45 nm |
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Fab![Plant which fabricates the semiconductor component Plant which fabricates the semiconductor component](icons/10x10/info_gray.gif) |
Texas Instruments |
Pins![Number of pins on the package Number of pins on the package](icons/10x10/info_gray.gif) |
515 pins |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
IMG PowerVR SGX530 GPU |
Number of GPU cores: |
1-core GPU |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Additional Information:
|
Special Features: Embedded 430MHz TI TMS320C64x DSP, Embedded image signal processor (12MP camera support), 2D/3D graphics acceleration (IVA 2), OpenGL ES 1.1, OpenGL ES 2.0, OpenVG, SmartReflex technologies, M-shield mobile security, ARM TrustZone, Composite and S-video TV output, XGA/WXGA 16M-color (24-bit definition).. ›› |
Datasheet Attributes:
|
Data Integrity |
Final |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2010-06-22 20:58 |