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Designer![]() |
SiRF |
Type: | titan GPS V5 |
Year Released: | 2007 |
Function![]() |
SoC |
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Width of Machine Word![]() |
32 bit |
Supported Instruction Set(s): | ARMv6 |
Pipeline Stages![]() |
8 pipeline stages |
Type of processor core(s)![]() |
ARM1136EJ-S |
Number of processor core(s): | single-core |
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Memory Interface(s): | SDRAM |
Data Bus Width![]() |
64 bit |
Number of data bus channels: | 1 ch |
Non-volatile Memory Data Bus Width![]() |
16 bit |
Non-volatile Memory Interface![]() |
Yes |
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Recommended Minimum Clock Frequency: | 600 MHz min. |
Recommended Maximum Clock Frequency: | 650 MHz max. |
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L1 Instruction Cache per Core![]() |
16 Kbyte I-Cache |
L1 Data Cache per Core![]() |
16 Kbyte D-Cache |
Total L2 Cache![]() |
128 Kbyte L2 |
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Semiconductor Technology: |
CMOS![]() |
Pins![]() |
477 pins |
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Embedded GPU![]() |
N/A |
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Supported Cellular Data Links![]() |
No |
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Special Features: 16-channel DMA, VFPU, AMBA 2.0 AHB, ARM Jazelle, integrated 40+ channels Centrality GPS V5 DSP |
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Data Integrity![]() |
Final |
Added![]() |
2007-09-08 19:02 |
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