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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component SiRF
Type titan GPS V5
Year Released 2007
FunctionMain function of the component  System-On-a-Chip

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv6
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 8 pipeline stages
Number of processor core(s) 1
Type of processor core(s)Type and allocation of processor core(s) ARM1136EJ-S

BusesBuses: 
Memory Interface(s):   SDRAM
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 64 bit
Number of data bus channels 1 ch
Non-volatile Memory Data Bus WidthMaximum selectable bit width of secondary data (non-volatile storage) bus of memory interface 16 bit
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  Yes
DMA ChannelsDMA (Direct Memory Access) allows direct data transfer between operative memory (RAM) and peripherals (hard disk, non-volatile storage, etc.) bypassing processor core. Multiple DMA channels allows parallel DMA operations. 16 ch


Clock FrequenciesClock Frequencies: 
Recommended Minimum Clock Frequency 600 MHz min.
Recommended Maximum Clock Frequency 650 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 16 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 16 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 128 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
PinsNumber of pins on the package 477 pins

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A

Cellular CommunicationCellular Communication: 

Supported Cellular Data LinksList of supported cellular data links  No

Satellite NavigationSatellite Navigation: 

Supported GPS protocol(s):   Yes

Additional InformationAdditional Information: 
Special Features 16-channel DMA, VFPU, AMBA 2.0 AHB, ARM Jazelle, integrated 40+ channels Centrality GPS V5 DSP

Datasheet AttributesDatasheet Attributes: 

Related Page URL
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2007-09-08 19:02
 
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