Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Spreadtrum |
Type: |
SC7715 |
Year Released: |
2013 |
Function |
Application Processor with Modem |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7-A |
Number of processor core(s): |
1 |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
ARM Cortex-A7 |
Buses:
|
Memory Interface(s): |
mobile (LP) DDR2 SDRAM |
Max. Clock Frequency of Memory IF![Clock frequency of fastest supported memory interface Clock frequency of fastest supported memory interface](icons/10x10/info_gray.gif) |
333 MHz |
Number of data bus channels: |
1 ch |
Non-volatile Memory Data Bus Width![Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface](icons/10x10/info_gray.gif) |
16 bit |
Non-volatile Memory Interface |
eMMC 4.5
, NAND Flash Interface |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
1200 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte D-Cache |
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
256 Kbyte L2 |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
40 nm |
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Supply Voltage: |
1.8 V |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
ARM Mali-400 GPU |
Number of GPU cores: |
1-core GPU |
Dedicated Graphics Memory![Dedicated operative memory (video RAM, VRAM) Dedicated operative memory (video RAM, VRAM)](icons/10x10/info_gray.gif) |
0.25 MiB |
Cellular Communication:
|
Supported Cellular Data Links |
GPRS (Class unspecified)
, GPRS Class 12
, EDGE (Class unspecified)
, EDGE Multi-slot Class 12
, UMTS 384 kbps (W-CDMA)
, HSUPA (Cat. unspecified)
, HSUPA 5.76 Mbps (Cat. 6)
, HSDPA (Cat. unspecified)
, HSPA+ 21.1 Mbps (Cat. 18) data links |
Communication Interfaces:
|
Supported USB Specification: |
No |
Bluetooth support |
No |
Wireless LAN support |
No |
Supported Audio/Video Interface: |
No |
Satellite Navigation:
|
Supported GPS protocol(s): |
No |
Additional Information:
|
Special Features: ARM Cortex-A7 Harvard processor core, 8/16-bit NAND flash interface, GPRS Class 12, EDGE Class 12, W-CDMA/UMTS, HSPA+ 21.1Mbps, HSUPA 5.76Mbps baseband support, ARM Mali-400MP1 GPU, tri-SIM / tri-standby support, WVGA display support, 5 MP camera support, USB OTG 2.0 interfaces |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2014-08-01 13:14 |