Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Marvell |
Type: |
ARMADA PXA2128 |
Year Released: |
2012 |
Function |
Multi-core Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7 |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
3x Marvell ARMv7 MPcore |
Number of processor core(s): |
tri-core |
Buses:
|
Memory Interface(s): |
LPDDR2 SDRAM
, DDR3L SDRAM
, LPDDR3 SDRAM |
Max. Clock Frequency of Memory IF![Clock frequency of fastest supported memory interface Clock frequency of fastest supported memory interface](icons/10x10/info_gray.gif) |
600 MHz |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
32 bit |
Number of data bus channels: |
2 ch |
Max. Data Rate![Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units.](icons/10x10/info_gray.gif) |
9.6 Gbyte/s |
Non-volatile Memory Interface |
eMMC 4.5
, NAND Flash Interface |
Clock Frequencies:
|
Recommended Minimum Clock Frequency: |
624 MHz min. |
Recommended Maximum Clock Frequency: |
1200 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte D-Cache |
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
512 Kbyte L2 |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
40 nm |
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
N/A |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Additional Information:
|
Special Features: Marvell Hybrid-SMP Technology, dual 1200 MHz ARMv7 HPM processor core, single 624 MHz ARMv7 LPM processor core, 32 Kbyte I-cache per core, 32 Kbyte I-cache per core, 512 Kbyte L2 cache, VFPv3.0-D32, ARM NEON, ARM Jazelle, ARM TrustZone, HDMI 1.3c.. ›› |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2013-12-19 10:39 |