Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Marvell |
Type: |
Armada 618 |
Year Released: |
2010 |
Function |
Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7 |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
Marvell Sheeva |
Number of processor core(s): |
single-core |
Buses:
|
Memory Interface(s): |
DDR SDRAM
, LPDDR SDRAM
, LPDDR2 SDRAM |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
32 bit |
Number of data bus channels: |
1 ch |
Non-volatile Memory Data Bus Width![Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface](icons/10x10/info_gray.gif) |
16 bit |
Non-volatile Memory Interface |
NAND Flash Interface |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
1000 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte D-Cache |
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
256 Kbyte L2 |
Technology and Packaging:
|
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
N/A |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Additional Information:
|
Special Features: Marvell Sheeva Superscalar processor core, VFPUv3, 8/16-bit eMMC (SLC/MLC) NAND Flash support, integrated 2D/3D GPU, 1080p H.264 30fps decode, 1080p 30fps H.264 encode,USB 2.0 host, USB 2.0 OTG, HDMI v1.3a TV out support, ISP, 16 MP camera support |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2012-12-20 17:12 |