Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Marvell |
Type: |
Armada 510 |
Year Released: |
2010 |
Function |
Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7, WMMX2 |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
Marvell Sheeva |
Number of processor core(s): |
single-core |
Buses:
|
Memory Interface(s): |
LPDDR SDRAM
, LPDDR3 SDRAM |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
32 bit |
Number of data bus channels: |
1 ch |
Non-volatile Memory Data Bus Width![Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface](icons/10x10/info_gray.gif) |
8 bit |
Non-volatile Memory Interface |
SATA![SATA revision 1.0 (2003) offering 1.5 Gbit/s data rate SATA revision 1.0 (2003) offering 1.5 Gbit/s data rate](icons/10x10/info_gray.gif) |
Clock Frequencies:
|
Recommended Minimum Clock Frequency: |
1200 MHz min. |
Recommended Maximum Clock Frequency: |
N/A |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte D-Cache |
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
512 Kbyte L2 |
Technology and Packaging:
|
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
N/A |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Additional Information:
|
Special Features: Marvell Sheeva Superscalar processor core, integrated FPU v.3, 32-bit LP-DDR/DDR2/DDR3 SD RAM interface, NAND Flash support, integrated Marvell GC600 2D/3D graphics engine, 1080p H.264 30fps Decode, 1080p 30fps H.264 Encode, Up to 8 megapixel camera support, USB 2.0 host, USB.. ›› |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2010-03-19 23:35 |