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Designer![]() |
Toshiba |
Type: | TMPR3922U |
Year Released: | 1998 |
Function![]() |
Application Processor |
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Width of Machine Word![]() |
32 bit |
Supported Instruction Set(s): | MIPS I, MIPS II |
Type of processor core(s)![]() |
MIPS R3000A (Toshiba TX3920) |
Number of processor core(s): | single-core |
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Memory Interface(s): | Yes |
Data Bus Width![]() |
32 bit |
Number of data bus channels: | 1 ch |
Non-volatile Memory Interface![]() |
No |
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Internal Systembus Clock: | 66 MHz |
Recommended Maximum Clock Frequency: | N/A |
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L1 Instruction Cache per Core![]() |
16 Kbyte I-Cache |
L1 Data Cache per Core![]() |
8 Kbyte D-Cache |
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Semiconductor Technology: |
CMOS![]() |
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Embedded GPU![]() |
N/A |
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Supported Cellular Data Links![]() |
No |
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Special Features: 32MB DRAM / 64MB ROM addressing |
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Data Integrity![]() |
Final |
Added![]() |
2006-01-01 06:00 |
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