Generel Characteristics: |
Designer |
Apple |
Type: |
A17 Pro APL1002 / APL1V02 |
Codename: |
T8130 |
Year Released: |
2023 |
Function |
Multi-core Application Processor |
Architecture: |
Width of Machine Word |
64 bit |
Supported Instruction Set(s): |
ARMv8.6-A (A32, A64) |
Type of processor core(s) |
2x Apple Coll P + 4x Apple Coll E cores |
Number of processor core(s): |
hexa-core |
Buses: |
Memory Interface(s): |
LPDDR4x SDRAM
, LPDDR5 SDRAM |
Max. Clock Frequency of Memory IF |
3200 MHz |
Data Bus Width |
16 bit |
Number of data bus channels: |
4 ch |
Max. Data Rate |
51.2 Gbyte/s |
Non-volatile Memory Interface |
moviNAND
, NAND Flash Interface
, SATA
, SATA II
, UFS 3.1
, UFS 3.1 2-lane
, UFS 4.0 |
Clock Frequencies: |
Recommended Maximum Clock Frequency: |
3780 MHz max. |
Cache Memories: |
L1 Instruction Cache per Core |
192 Kbyte I-Cache |
L1 Data Cache per Core |
128 Kbyte D-Cache |
Total L2 Cache |
20480 Kbyte L2 |
Total L3 Cache: |
24576 Kbyte L3 |
Technology and Packaging: |
Feature Size |
3 nm |
Semiconductor Technology: |
FinFET |
Number of Transistors Integrated: |
19000000000 |
Fab |
TSMC |
Graphical Subsystem: |
Embedded GPU |
Apple G16P GPU |
Number of GPU cores: |
6-core GPU |
GPU Clock: |
1398 MHz GPU |
Cellular Communication: |
Supported Cellular Data Links |
No |
Additional Information: |
Special Features: 2x high-performance 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3.78 GHz, 192 KB L1 data cache per core, 128 KB L1 instruction cache per core, 8 MiB L2 cache per core) + 4x high-efficiency 64-bit ARMv8-compatible (AArch32-AArch64) Harvard.. ›› |
Datasheet Attributes: |
Data Integrity |
Preliminary |
Added |
2023-11-22 12:39 |