Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Intel |
Type: |
Atom x5-Z8350 |
Codename: |
Cherry Trail |
Year Released: |
2016 |
Function |
Multi-core Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
64 bit |
Supported Instruction Set(s): |
IA-32 (x86), IA-64 (x64), SSE4, SSE 4.1, SSE 4.2 |
Number of processor core(s): |
4 |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
4x Intel Airmont |
Buses:
|
Memory Interface(s): |
DDR3L (LV) SDRAM
, DDR3L-RS SDRAM |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
64 bit |
Number of data bus channels: |
1 ch |
Non-volatile Memory Interface |
Yes |
Clock Frequencies:
|
Recommended Minimum Clock Frequency: |
1440 MHz min. |
Recommended Maximum Clock Frequency: |
1920 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
24 Kbyte D-Cache |
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
2048 Kbyte L2 |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
14 nm |
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Fab![Plant which fabricates the semiconductor component Plant which fabricates the semiconductor component](icons/10x10/info_gray.gif) |
Intel |
Pins![Number of pins on the package Number of pins on the package](icons/10x10/info_gray.gif) |
592 pins |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
Intel HD Graphics 400 GPU |
Number of GPU cores: |
12-core GPU |
GPU Clock: |
200 MHz GPU |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Communication Interfaces:
|
Supported USB Specification: |
No |
Bluetooth support |
No |
Wireless LAN support |
No |
Supported Audio/Video Interface: |
No |
Satellite Navigation:
|
Supported GPS protocol(s): |
No |
Additional Information:
|
Special Features: 1.44 GHz Quad Intel Airmont processor cores, 32 Kbyte 8-way instruction cache per core, 24 Kbyte 6-way data cache per core, 512 Kbyte L2 cache per core, 64-bit 800 MHz DDR3L-RS 1600 SD RAM interface (max. 12.8 GB/s), 12-core 200 MHz Intel HD Graphics 400 Gen8-LP GPU EU12 (max. 500 MHz), dual display support, DirectX 11.1 support, OpenGL 4.3, OpenGL ES 3.0, OpenCL 1.2, Intel Clear Video HD Technology, Intel Wireless Display, Intel Insider, Image Signal Processor, USB 3.0 |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2016-02-21 22:54 |