Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Samsung |
Type: |
Exynos 4 Quad 4415 |
Year Released: |
2014 |
Function |
Multi-core Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7 |
Pipeline Stages![Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions.](icons/10x10/info_gray.gif) |
8 pipeline stages |
Number of processor core(s): |
4 |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
4x ARM Cortex-A9 MPcore |
Buses:
|
Memory Interface(s): |
mobile (LP) DDR2 SDRAM
, mobile (LP) DDR3 SDRAM |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
32 bit |
Number of data bus channels: |
1 ch |
Non-volatile Memory Interface |
moviNAND
, NAND Flash Interface
, SATA![SATA revision 1.0 (2003) offering 1.5 Gbit/s data rate SATA revision 1.0 (2003) offering 1.5 Gbit/s data rate](icons/10x10/info_gray.gif) |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
N/A |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte D-Cache |
Technology and Packaging:
|
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Fab![Plant which fabricates the semiconductor component Plant which fabricates the semiconductor component](icons/10x10/info_gray.gif) |
Samsung |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
ARM Mali-400 GPU |
Number of GPU cores: |
4-core GPU |
GPU Clock: |
533 MHz GPU |
Dedicated Graphics Memory![Dedicated operative memory (video RAM, VRAM) Dedicated operative memory (video RAM, VRAM)](icons/10x10/info_gray.gif) |
0.25 MiB |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Communication Interfaces:
|
Supported USB Specification: |
No |
Bluetooth support |
No |
Wireless LAN support |
No |
Supported Audio/Video Interface: |
No |
Satellite Navigation:
|
Supported GPS protocol(s): |
Yes |
Additional Information:
|
Special Features: quad ARM Cortex-A9 Harvard Superscalar processor core, 64/32-bit Multi-layer AHB/AXI bus, ARM TrustZone, ARM NEON SIMD engine, LPDDR2, LP-DDR3 SDRAM interface, NAND flash, moviNAND, SATA, eMMC interface, embedded GPS module, HDMI 1.4, triple display controller, stereoscopic video encode, 1080p video encode, 1080p video decode, audio subsystem, 533 MHz ARM Mali-400MP4 GPU |
Datasheet Attributes:
|
Data Integrity |
Incomplete |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2014-10-26 12:01 |