Generel Characteristics:
|
Designer![Company which designed the semiconductor component Company which designed the semiconductor component](icons/10x10/info_gray.gif) |
Rockchip |
Type: |
RK3288 |
Year Released: |
2014 |
Function |
Multi-core Application Processor |
Architecture:
|
Width of Machine Word![Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.](icons/10x10/info_gray.gif) |
32 bit |
Supported Instruction Set(s): |
ARMv7-A |
Number of processor core(s): |
4 |
Type of processor core(s)![Type and allocation of processor core(s) Type and allocation of processor core(s)](icons/10x10/info_gray.gif) |
4x ARM Cortex-A17 MPcore |
Buses:
|
Memory Interface(s): |
mobile (LP) DDR2 SDRAM
, DDR3 SDRAM
, mobile (LP) DDR3 SDRAM |
Data Bus Width![Maximum selectable bit width of primary data bus (RAM) of memory interface Maximum selectable bit width of primary data bus (RAM) of memory interface](icons/10x10/info_gray.gif) |
32 bit |
Number of data bus channels: |
2 ch |
Non-volatile Memory Data Bus Width![Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface Maximum selectable bit width of secondary data (non-volatile storage) bus of memory interface](icons/10x10/info_gray.gif) |
16 bit |
Non-volatile Memory Interface |
eMMC 4.5
, NAND Flash Interface |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
N/A |
Cache Memories:
|
L1 Instruction Cache per Core![Capacity of level 1 instruction cache per processor core Capacity of level 1 instruction cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte I-Cache |
L1 Data Cache per Core![Capacity of level 1 data cache per processor core Capacity of level 1 data cache per processor core](icons/10x10/info_gray.gif) |
32 Kbyte D-Cache |
Total L2 Cache![Capacity of level 2 cache shared between processor core(s) Capacity of level 2 cache shared between processor core(s)](icons/10x10/info_gray.gif) |
1024 Kbyte L2 |
Technology and Packaging:
|
Feature Size![The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology](icons/10x10/info_gray.gif) |
28 nm |
Semiconductor Technology: |
CMOS![Complementary Metal-oxide - Semiconductor Field Effect Transistor Complementary Metal-oxide - Semiconductor Field Effect Transistor](icons/10x10/info_gray.gif) |
Graphical Subsystem:
|
Embedded GPU![Manufactuer (or IP designer) and type of embedded graphics coprocessor(s). Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).](icons/10x10/info_gray.gif) |
ARM Mali-T760 GPU |
Number of GPU cores: |
1-core GPU |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Communication Interfaces:
|
Supported USB Specification: |
No |
Bluetooth support |
No |
Wireless LAN support |
No |
Supported Audio/Video Interface: |
No |
Satellite Navigation:
|
Supported GPS protocol(s): |
No |
Additional Information:
|
Special Features: quad ARM Cortex-A17 Harvard Superscalar CPU core, 32 Kbyte I-Cache per core, 32 Kbyte D-Cache per core, dual-channel 8-bit SLC/MLC/TLC NAD Flash interface, ARM NEON SIMD engine, OpenVG 1.1, OpenGL ES 1.1/2.0/3.0, OpenCL 1.1, Renderscript, Directx11 support, 2160p video decode, 1080p video encode, 1080p HDMI 1.4,USB 2.0 host interface, 13 MP camea support, 2K HDMI 2.0, USB 2.0 OTG, 2x USB2.0 Host, 100M/1000M RMII/RGMII Ethernet interface |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added![The exact time of the datasheet addition The exact time of the datasheet addition](icons/10x10/info_gray.gif) |
2014-04-29 21:42 |