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Processor Specs: Referred (not editable) comparison sheet [2]

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Qualcomm Snapdragon 805 APQ8084 (8084 Fusion 4)
Qualcomm Snapdragon 801 APQ8074AB v3
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Qualcomm Snapdragon 805 APQ8084  (8084 Fusion 4)
Qualcomm Snapdragon 801 APQ8074AB v3
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Generel CharacteristicsGenerel Characteristics
Year Released 2014 2014
FunctionMain function of the component Multi-core Application Processor Multi-core Application Processor

ArchitectureArchitecture
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit 32 bit
Supported Instruction Set(s) ARMv7-A ARMv7
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 11 pipeline stages 11 pipeline stages
Type of processor core(s)Type and allocation of processor core(s) 4x Qualcomm Krait 450 4x Qualcomm Krait 400
Number of processor core(s) quad-core quad-core

BusesBuses
Memory Interface(s) LPDDR3 SDRAM LPDDR3 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 800 MHz 933 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 16 bit 32 bit
Number of data bus channels 4 ch 2 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 12.8 Gbyte/s 14.93 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory eMMC 5.0 eMMC 5.0

Clock FrequenciesClock Frequencies
Recommended Maximum Clock Frequency 2500 MHz max. 2265 MHz max.

Cache MemoriesCache Memories
L0 Instruction Cache per CoreCapacity of level 0 instruction cache per processor core 4 Kbyte L0 I-Cache
L0 Data Cache per CoreCapacity of level 0 data cache per processor core 4 Kbyte L0 D-Cache
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 16 Kbyte I-Cache 16 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 16 Kbyte D-Cache 16 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 2048 Kbyte L2 2048 Kbyte L2



Technology and PackagingTechnology and Packaging
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 28 nm 28 nm
Semiconductor Technology CMOS CMOS
FabPlant which fabricates the semiconductor component TSMC TSMC

Graphical SubsystemGraphical Subsystem
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). Qualcomm Adreno 420 GPU Qualcomm Adreno 330 GPU
GPU Clock 500 MHz GPU 578 MHz GPU
Dedicated Graphics MemoryDedicated operative memory (video RAM, VRAM) 1.5 MiB 1 MiB

Cellular CommunicationCellular Communication

Additional InformationAdditional Information
Special Features 4x Qualcomm Krait 450 Harvard Superscalar processor core, Hexagon V50 DSP, OpenGL ES 3.0, OpenCL 1.2, OpenVG 1.1, EGL 3.1, DirectX 11, 55 MP camera support, Stereoscopic 3D Kit, 2160p video encode/decode, Qualcomm iZAT Gen8B with GLONASS, BeiDou, USB 3.0,.. 4x Qualcomm Krait 400 Harvard Superscalar processor core, 465 MHz ISP, 55 MP camera support, Stereoscopic 3D Kit, 2160p video encode/decode, gpsOneGen 8B with GLONASS, USB 3.0, OpenGL ES 3.0, OpenCL 1.1, OpenVG 1.1, EGL 3.1, DirectX 11. Snapdragon 800..

Datasheet AttributesDatasheet Attributes
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b Preliminary Preliminary
AddedThe exact time of the datasheet addition 2013-11-21 11:35 2014-02-26 16:41

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