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Processor Specs: Referred (not editable) comparison sheet [2]

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Apple A5 APL0498 (S5L8940)

Apple A5X APL5498 (S5L8945X)

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Generel Characteristics

Year Released

2011

2012

Function Main function of the component

SoC

Architecture

Width of Machine Word Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.

32 bit

Supported Instruction Set(s)

ARMv7

Pipeline Stages Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions.

8 pipeline stages

Type of processor core(s) Type and allocation of processor core(s)

2x ARM Cortex-A9 MPcore

Number of processor core(s)

dual-core

Buses

Memory Interface(s)

LPDDR2 SDRAM

Max. Clock Frequency of Memory IF Clock frequency of fastest supported memory interface

533 MHz

400 MHz

Data Bus Width Maximum selectable bit width of primary data bus (RAM) of memory interface

64 bit

32 bit

Number of data bus channels

1 ch

Max. Data Rate Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units.

8.53 Gbyte/s

3.2 Gbyte/s

Non-volatile Memory Interface Interface which determines physical layer towards the NV memory

eMMC 5.1, moviNAND, NAND Flash Interface, SATA

moviNAND, NAND Flash Interface, SATA

Clock Frequencies

Recommended Minimum Clock Frequency

800 MHz min.

Recommended Maximum Clock Frequency

1200 MHz max.

1000 MHz max.

Cache Memories

L1 Instruction Cache per Core Capacity of level 1 instruction cache per processor core

32 Kbyte I-Cache

L1 Data Cache per Core Capacity of level 1 data cache per processor core

32 Kbyte D-Cache

Total L2 Cache Capacity of level 2 cache shared between processor core(s)

512 Kbyte L2

1024 Kbyte L2

Technology and Packaging

Feature Size The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology

45 nm

Semiconductor Technology

CMOS

Fab

Samsung

Graphical Subsystem

Embedded GPU Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).

IMG PowerVR SGX543 GPU

Number of GPU cores

2-core GPU

4-core GPU

GPU Clock

250 MHz GPU

Cellular Communication

Additional Information

Special Features

dual ARM Cortex-A9 Harvard Superscalar processor core, 64/32-bit Multi-layer AHB/AXI bus, ARM TrustZone, ARM NEON SIMD engine, 512MB dual-channel (64-bit) 266 MHz LPDDR2-1066 SDRAM, NAND flash, moviNAND, SATA, eMMC interface, embedded GPS module, HDMI, triple display controller, 1080p video encode,..

dual ARM Cortex-A9 Harvard Superscalar processor core, 64/32-bit Multi-layer AHB/AXI bus, ARM TrustZone, ARM NEON SIMD engine, 400 MHz 32-bit LPDDR2 SDRAM interface, NAND flash, moviNAND, SATA, eMMC interface, embedded GPS module, HDMI, triple display controller, 1080p video encode, 1080p..

Datasheet Attributes

Data Integrity Data integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b

Preliminary

Added

2011-03-05 10:58

2012-03-07 21:50