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Processor Specs: Referred (not editable) comparison sheet [3]

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HiSilicon Honor KIRIN980
HiSilicon Honor KIRIN9000 5G
HiSilicon Honor KIRIN9000E 5G
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HiSilicon Honor KIRIN980
HiSilicon Honor KIRIN9000 5G
HiSilicon Honor KIRIN9000E 5G
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Generel CharacteristicsGenerel Characteristics
Year Released 2018 2020 2020
FunctionMain function of the component Multi-core Application Processor with Modem Multi-core Application Processor with Modem Multi-core Application Processor with Modem

ArchitectureArchitecture
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit 64 bit 64 bit
Supported Instruction Set(s) ARMv8.2-A ARMv8.3 (A32, A64) ARMv8.3 (A32, A64)
Type of processor core(s)Type and allocation of processor core(s) 4x ARM Cortex-A76 + 4x ARM Cortex-A55 MPcore 4x ARM Cortex-A77 + 4x ARM Cortex-A55 MPcore 4x ARM Cortex-A77 + 4x ARM Cortex-A55 MPcore
Number of processor core(s) octa-core octa-core octa-core

BusesBuses
Memory Interface(s) LPDDR4x SDRAM LPDDR4x SDRAM, LPDDR5 SDRAM LPDDR4x SDRAM, LPDDR5 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 2133 MHz 2750 MHz 2750 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 16 bit 16 bit 16 bit
Number of data bus channels 4 ch 4 ch 4 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 34.13 Gbyte/s 44 Gbyte/s 44 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory eMMC 5.1, UFS 2.1 UFS 3.1 UFS 3.1

Clock FrequenciesClock Frequencies
Recommended Maximum Clock Frequency 2600 MHz max. 3130 MHz max. 3130 MHz max.

Cache MemoriesCache Memories
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 2560 Kbyte L2
Total L3 Cache 4096 Kbyte L3



Technology and PackagingTechnology and Packaging
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 7 nm 5 nm 5 nm
Semiconductor Technology CMOS CMOS CMOS
Number of Transistors Integrated 6900000000 15300000000 15300000000
FabPlant which fabricates the semiconductor component TSMC TSMC TSMC

Graphical SubsystemGraphical Subsystem
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). ARM Mali-G76 GPU ARM Mail-G78 GPU ARM Mail-G78 GPU
Number of GPU cores 10-core GPU 24-core GPU 22-core GPU
GPU Clock 720 MHz GPU 760 MHz GPU

Cellular CommunicationCellular Communication
Supported Cellular Data LinksList of supported cellular data links CSD, GPRS, GPRS C12, GPRS MSC33, EDGE, EDGE MSC12, UMTS, HSUPA, HSUPA 1.4, HSUPA 2.0, HSUPA 5.8, HSUPA 11.5, HSDPA, HSDPA 1.8, HSDPA 3.6, HSDPA 7.2, HSDPA 10.2, HSDPA 14.4, HSPA+ 21.1, HSPA+ 28.8, HSPA+ 42.2, DC-HSDPA 42.2, cdmaOne, CDMA2000 1x, CDMA2000 1xEV-DO, CDMA2000 1xEV-DO Rev A, TD-SCDMA, TD-HSDPA, LTE, LTE 50/25, LTE 75/25, LTE 100/50, LTE 150/50, LTE 225/50, LTE 300/50, LTE 300/75, LTE 300/100, LTE 400/150, LTE 450/50, LTE 450/100, LTE 600/50, LTE 600/100, LTE 750/225, LTE 1000/100, LTE 1200/200, LTE 1400/300 data links CSD, GPRS, GPRS C12, GPRS MSC33, EDGE, EDGE MSC12, UMTS, HSUPA, HSUPA 1.4, HSUPA 2.0, HSUPA 5.8, HSUPA 11.5, HSDPA, HSDPA 1.8, HSDPA 3.6, HSDPA 7.2, HSDPA 10.2, HSDPA 14.4, HSPA+ 21.1, HSPA+ 28.8, HSPA+ 42.2, DC-HSDPA 42.2, cdmaOne, CDMA2000 1x, CDMA2000 1xEV-DO, CDMA2000 1xEV-DO Rev A, TD-SCDMA, TD-HSDPA, LTE, LTE 50/25, LTE 75/25, LTE 100/50, LTE 150/50, LTE 225/50, LTE 300/50, LTE 300/75, LTE 300/100, LTE 400/150, LTE 450/50, LTE 450/100, LTE 600/50, LTE 600/100, LTE 750/225, LTE 1000/100, LTE 1200/200, LTE 1400/300, LTE 1600, LTE 2000/300, LTE 2400/400, NR 1500, NR 2600, NR 3700, NR 4600 data links CSD, GPRS, GPRS C12, GPRS MSC33, EDGE, EDGE MSC12, UMTS, HSUPA, HSUPA 1.4, HSUPA 2.0, HSUPA 5.8, HSUPA 11.5, HSDPA, HSDPA 1.8, HSDPA 3.6, HSDPA 7.2, HSDPA 10.2, HSDPA 14.4, HSPA+ 21.1, HSPA+ 28.8, HSPA+ 42.2, DC-HSDPA 42.2, cdmaOne, CDMA2000 1x, CDMA2000 1xEV-DO, CDMA2000 1xEV-DO Rev A, TD-SCDMA, TD-HSDPA, LTE, LTE 50/25, LTE 75/25, LTE 100/50, LTE 150/50, LTE 225/50, LTE 300/50, LTE 300/75, LTE 300/100, LTE 400/150, LTE 450/50, LTE 450/100, LTE 600/50, LTE 600/100, LTE 750/225, LTE 1000/100, LTE 1200/200, LTE 1400/300, LTE 1600, LTE 2000/300, LTE 2400/400, NR 1500, NR 2600, NR 3700, NR 4600 data links

Additional InformationAdditional Information
Special Features dual ARM Cortex-A76 (up to 2.6 GHz, 512 Kbyte L2 cache per core) + dual ARM Cortex-A76 (up to 1.92 GHz, 512 Kbyte L2 cache per core) + quad ARM Cortex-A55 (up to 1.8 GHz, 128 Kbyte L2 cache per.. single ARM Cortex-A77 (up to 3.13 GHz) + triple ARM Cortex-A77 (up to 2.54 GHz) + quad ARM Cortex-A55 (up to 2.05 GHz) Harvard Superscalar processor cores, ARM big.LITTLE, HMP, GSM / GPRS Class 33 / EDGE / CDMA /.. single ARM Cortex-A77 (up to 3.13 GHz) + triple ARM Cortex-A77 (up to 2.54 GHz) + quad ARM Cortex-A55 (up to 2.05 GHz) Harvard Superscalar processor cores, ARM big.LITTLE, HMP, GSM / GPRS Class 33 / EDGE / CDMA /..

Datasheet AttributesDatasheet Attributes
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b Preliminary Preliminary Preliminary
AddedThe exact time of the datasheet addition 2018-09-11 22:19 2020-10-30 21:30 2020-11-03 22:04

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