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Processor Specs: Referred (not editable) comparison sheet [7]

If you would like to add more datasheets to the comparison table you can still find and add them around the site while browsing, querying or searching Processor Specs. Meanwhile you will not lose the comparison table below. Furthermore unnecassary datasheets can be removed by clicking on the "Remove from comparison" buttons (ever more than one item during one page load) but in this case reloading the table will be needed. Then click again on the appropriate header "Compare" button.
Apple A13 Bionic APL1085 / APL1W85 (T8030)
Apple M1 APL1102 / APL1W02 (T8103)
Apple M1 Pro APL1103 / APL1W03 (T6000)
Apple M1 Max Lite APL1105 / APL1W05 (T6001)
Apple M1 Lite APL1102 / APL1W02 (T8103)
Apple M1 Pro Lite APL1103 / APL1W03 (T6000)
Apple M1 Max APL1105 / APL1W05 (T6001)
Use the following link to refer to this comparison
 Apple A13 Bionic APL1085 / APL1W85 (T8030)
 		Apple M1 APL1102 / APL1W02 (T8103)
 		Apple M1 Pro APL1103 / APL1W03 (T6000)
 		Apple M1 Max Lite APL1105 / APL1W05 (T6001)
 		Apple M1 Lite APL1102 / APL1W02 (T8103)
 		Apple M1 Pro Lite APL1103 / APL1W03 (T6000)
 		Apple M1 Max APL1105 / APL1W05 (T6001)
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Generel CharacteristicsGenerel Characteristics
Year Released 2019 2020 2021 2021 2020 2021 2021
FunctionMain function of the component Application Processor Application Processor SoC SoC Application Processor SoC SoC

ArchitectureArchitecture
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit 64 bit 64 bit 64 bit 64 bit 64 bit 64 bit
Supported Instruction Set(s) ARMv8.4-A (A32, A64) ARMv8.6-A (A32, A64) ARMv8.6-A (A32, A64) ARMv8.6-A (A32, A64) ARMv8.6-A (A32, A64) ARMv8.6-A (A32, A64) ARMv8.6-A (A32, A64)
Type of processor core(s)Type and allocation of processor core(s) 2x Apple Lightning + 4x Apple Thunder cores 4x Apple Firestorm + 4x Apple Icestorm cores 8x Apple Firestorm + 2x Apple Icestorm cores 8x Apple Firestorm + 2x Apple Icestorm cores 4x Apple Firestorm + 4x Apple Icestorm cores 6x Apple Firestorm + 2x Apple Icestorm cores 8x Apple Firestorm + 2x Apple Icestorm cores
Number of processor core(s) hexa-core octa-core octa-core octa-core octa-core octa-core octa-core

BusesBuses
Memory Interface(s) LPDDR4x SDRAM LPDDR4x SDRAM LPDDR5 SDRAM LPDDR5 SDRAM LPDDR4x SDRAM LPDDR5 SDRAM LPDDR5 SDRAM
Address Bus WidthMaximum selectable bit width of address bus of memory interface 32 bit 32 bit 32 bit 32 bit
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 2133 MHz 3200 MHz 3200 MHz 2133 MHz 3200 MHz 3200 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 64 bit 64 bit 64 bit 64 bit 64 bit 64 bit 64 bit
Number of data bus channels 2 ch 2 ch 4 ch 8 ch 2 ch 4 ch 8 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 68.26 Gbyte/s 204.8 Gbyte/s 409.6 Gbyte/s 68.26 Gbyte/s 204.8 Gbyte/s 409.6 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory eMMC 5.1, moviNAND, NAND Flash Interface, SATA, UFS 3.0 eMMC 5.1, moviNAND, NAND Flash Interface, SATA, SATA II, SATA III, UFS 3.1, UFS 3.1 2-lane eMMC 5.1, moviNAND, NAND Flash Interface, SATA, SATA II, SATA III, UFS 3.1, UFS 3.1 2-lane eMMC 5.1, moviNAND, NAND Flash Interface, SATA, SATA II, SATA III, UFS 3.1, UFS 3.1 2-lane eMMC 5.1, moviNAND, NAND Flash Interface, SATA, SATA II, SATA III, UFS 3.1, UFS 3.1 2-lane eMMC 5.1, moviNAND, NAND Flash Interface, SATA, SATA II, SATA III, UFS 3.1, UFS 3.1 2-lane eMMC 5.1, moviNAND, NAND Flash Interface, SATA, SATA II, SATA III, UFS 3.1, UFS 3.1 2-lane

Clock FrequenciesClock Frequencies
Recommended Minimum Clock Frequency 600 MHz min. 600 MHz min. 600 MHz min. 600 MHz min.
Recommended Maximum Clock Frequency 2660 MHz max. 3228 MHz max. 3228 MHz max. 3228 MHz max. 3228 MHz max. 3228 MHz max. 3228 MHz max.

Cache MemoriesCache Memories
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 128 Kbyte I-Cache 192 Kbyte I-Cache 192 Kbyte I-Cache 192 Kbyte I-Cache 192 Kbyte I-Cache 192 Kbyte I-Cache 192 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 128 Kbyte D-Cache 128 Kbyte D-Cache 128 Kbyte D-Cache 128 Kbyte D-Cache 128 Kbyte D-Cache 128 Kbyte D-Cache 128 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 4096 Kbyte L2 16384 Kbyte L2 28672 Kbyte L2 28672 Kbyte L2 16384 Kbyte L2 28672 Kbyte L2 28672 Kbyte L2
Total L3 Cache 16384 Kbyte L3 24576 Kbyte L3 49152 Kbyte L3 16384 Kbyte L3 24576 Kbyte L3 49152 Kbyte L3



Technology and PackagingTechnology and Packaging
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 7 nm 5 nm 5 nm 5 nm 5 nm 5 nm 5 nm
Semiconductor Technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Number of Transistors Integrated 8500000000 16000000000 33700000000 57000000000 16000000000 33700000000 57000000000
FabPlant which fabricates the semiconductor component TSMC TSMC TSMC TSMC TSMC TSMC TSMC

Graphical SubsystemGraphical Subsystem
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). Apple A13 GPU Apple M1 GPU Apple M1 Pro GPU Apple M1 Max GPU Apple M1 GPU Apple M1 Pro GPU Apple M1 Max GPU
Number of GPU cores 4-core GPU 8-core GPU 16-core GPU 24-core GPU 7-core GPU 14-core GPU 32-core GPU
GPU Clock 1278 MHz GPU 1296 MHz GPU 1296 MHz GPU 1278 MHz GPU 1296 MHz GPU 1296 MHz GPU

Cellular CommunicationCellular Communication

Additional InformationAdditional Information
Special Features 2x high-performance Apple Lightning 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 2660 MHz, 128 KB L1 data cache per core, 128 KB L1 instruction cache per core) + 4x high-efficiency Apple Thunder 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor.. 4x high-performance Apple Firestorm 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3228 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 12 MiB shared L2 cache) + 4x high-efficiency Apple.. 8x high-performance Apple Firestorm 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3228 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 24 MiB shared L2 cache) + 2x high-efficiency Apple.. 8x high-performance Apple Firestorm 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3228 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 24 MiB shared L2 cache) + 2x high-efficiency Apple.. 4x high-performance Apple Firestorm 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3228 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 12 MiB shared L2 cache) + 4x high-efficiency Apple.. 6x high-performance Apple Firestorm 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3228 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 24 MiB shared L2 cache) + 2x high-efficiency Apple.. 8x high-performance Apple Firestorm 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3228 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 24 MiB shared L2 cache) + 2x high-efficiency Apple..

Datasheet AttributesDatasheet Attributes
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b Preliminary Final Final Final Final Final Final
AddedThe exact time of the datasheet addition 2019-09-12 12:14 2021-05-15 22:01 2022-07-05 11:19 2022-07-05 12:17 2022-07-05 15:00 2022-07-05 15:06 2022-07-05 15:19

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