 Generel Characteristics:
|
Designer |
Apple |
| Type: |
M3 Pro APL1203 |
| Codename: |
T6030 |
| Year Released: |
2023 |
| Function |
Multi-core Application Processor |
 Architecture:
|
| Width of Machine Word |
64 bit |
| Supported Instruction Set(s): |
ARMv8.6-A (A32, A64) |
| Type of processor core(s) |
6x Apple Everest + 6x Apple Sawtooth cores |
| Number of processor core(s): |
multi-core |
 Buses:
|
| Memory Interface(s): |
LPDDR5 SDRAM |
| Address Bus Width |
32 bit |
| Max. Clock Frequency of Memory IF |
3200 MHz |
| Data Bus Width |
64 bit |
| Number of data bus channels: |
3 ch |
| Max. Data Rate |
153.6 Gbyte/s |
| Non-volatile Memory Interface |
eMMC 5.1
, moviNAND
, NAND Flash Interface
, SATA
, SATA II
, SATA III
, UFS 3.1
, UFS 3.1 2-lane |
 Clock Frequencies:
|
| Recommended Maximum Clock Frequency: |
4050 MHz max. |
 Cache Memories:
|
| L1 Instruction Cache per Core |
192 Kbyte I-Cache |
| L1 Data Cache per Core |
128 Kbyte D-Cache |
| Total L2 Cache |
30720 Kbyte L2 |
| Total L3 Cache: |
12288 Kbyte L3 |
 Technology and Packaging:
|
| Feature Size |
3 nm |
| Semiconductor Technology: |
FinFET |
| Number of Transistors Integrated: |
37000000000 |
| Fab |
TSMC |
 Graphical Subsystem:
|
| Embedded GPU |
Apple M3 GPU |
| Number of GPU cores: |
18-core GPU |
 Cellular Communication:
|
| Supported Cellular Data Links |
No |
 Additional Information:
|
Special Features:
4x high-performance 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 4050 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 24 MiB shared L2 cache) + 4x high-efficiency 64-bit ARMv8-compatible (AArch32-AArch64).. ›› |
 Datasheet Attributes:
|
| Data Integrity |
Final |
| Added |
2024-07-10 23:30 |
All details | 
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