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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Apple
Type M3 APL1201
Codename T8122
Year Released 2023
FunctionMain function of the component  Multi-core Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit
Supported Instruction Set(s) ARMv8.6-A (A32, A64)
Type of processor core(s)Type and allocation of processor core(s) 4x Apple Everest + 4x Apple Sawtooth cores
Number of processor core(s) octa-core

BusesBuses: 
Memory Interface(s):   LPDDR5 SDRAM
Address Bus WidthMaximum selectable bit width of address bus of memory interface 32 bit
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 3200 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 64 bit
Number of data bus channels 2 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 102.4 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  eMMC 5.1Complies with embedded MMC 5.1 specification released in 2015 , moviNANDmoviNAND is a multimedia card (MMC) controller and onboard firmware developed by Samsung in 2006 , NAND Flash Interface , SATASATA revision 1.0 (2003) offering 1.5 Gbit/s data rate , SATA IISerial AT Attachment revision 2.0 (released in 2004) or 2.x offering 3 Gbit/s data rate , SATA IIISerial ATA revision 3.0 (released in 2004) or 3.x with 6 Gbit/s data rate , UFS 3.1UFS 3.1 (released as JESD220E in 2020) defines single-lane 1.45 GB/s or dual-lane 2.9 GB/s NAND flash EEPROM interface , UFS 3.1 2-laneComplies with dual-lane Universal Flash Storage 3.1 revision offering 2.9 GB/s NAND flash data rate


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 4050 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 192 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 128 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 20480 Kbyte L2
Total L3 Cache 8192 Kbyte L3

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 3 nm
Semiconductor Technology:   FinFETMultigate (usually double-gate) MOSFET transistor technology
Number of Transistors Integrated 25000000000
FabPlant which fabricates the semiconductor component TSMC

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). Apple M3 GPU
Number of GPU cores 10-core GPU
GPU Clock 1380 MHz GPU

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Additional InformationAdditional Information: 
Special Features
4x high-performance 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 4050 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 16 MiB shared L2 cache) + 4x high-efficiency 64-bit ARMv8-compatible (AArch32-AArch64).. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2024-07-10 19:57
 
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