Generel Characteristics: |
Designer |
Samsung |
Type: |
Google Tensor G3 GS301 S5P9865 |
Codename: |
Zuma |
Year Released: |
2023 |
Function |
Multi-core Application Processor with Modem |
Architecture: |
Width of Machine Word |
64 bit |
Supported Instruction Set(s): |
ARMv9-A (A32, A64) |
Type of processor core(s) |
1x ARM Cortex-X3 + 4x ARM Cortex-A715 + 4x ARM Cortex-A510 MPcores |
Number of processor core(s): |
multi-core |
Buses: |
Memory Interface(s): |
LPDDR5X SDRAM |
Max. Clock Frequency of Memory IF |
4266 MHz |
Data Bus Width |
16 bit |
Number of data bus channels: |
4 ch |
Max. Data Rate |
68.26 Gbyte/s |
Non-volatile Memory Interface |
UFS 3.1
, UFS 4.0 |
Clock Frequencies: |
Recommended Minimum Clock Frequency: |
324 MHz min. |
Recommended Maximum Clock Frequency: |
2914 MHz max. |
Cache Memories: |
Total L2 Cache |
2560 Kbyte L2 |
Total L3 Cache: |
8192 Kbyte L3 |
Technology and Packaging: |
Feature Size |
4 nm |
Semiconductor Technology: |
FinFET |
Fab |
Samsung |
Graphical Subsystem: |
Embedded GPU |
ARM Mali-G715 GPU |
Number of GPU cores: |
7-core GPU |
GPU Clock: |
890 MHz GPU |
Cellular Communication: |
Supported Cellular Data Links |
GPRS
, GPRS C10
, GPRS C12
, GPRS MSC10
, GPRS MSC12
, GPRS MSC32
, GPRS MSC33
, EDGE
, EDGE MSC10
, EDGE MSC12
, EDGE MSC32
, UMTS
, HSUPA
, HSUPA 1.4
, HSUPA 2.0
, HSUPA 5.8
, HSUPA 11.5
, HSDPA
, HSDPA 1.8
, HSDPA 3.6
, HSDPA 7.2
, HSDPA 10.2
, HSDPA 14.4
, HSPA+ 21.1
, HSPA+ 28.8
, HSPA+ 42.2
, DC-HSDPA 42.2
, cdmaOne
, CDMA2000 1x
, CDMA2000 1xEV-DO
, TD-SCDMA
, TD-HSDPA
, LTE
, LTE 50/25
, LTE 75/25
, LTE 100/50
, LTE 150/50
, LTE 225/50
, LTE 300/50
, LTE 300/75
, LTE 300/100
, LTE 400/150
, LTE 450/50
, LTE 450/100
, LTE 600/50
, LTE 600/100
, LTE 750/225
, LTE 1000/100
, LTE 1200/200
, LTE 1400/300
, LTE 1600
, LTE 2000/300
, LTE 2400/400
, LTE 2700/500
, LTE 3000/600
, NR 1500
, NR 2600
, NR 3700
, NR 4600
, NR 7500
, NR 10G data links |
Additional Information: |
Special Features: single ARM Cortex-X3 (up to 2.91 GHz, 1 Mbyte L2 cache) + quad ARM Cortex-A715 (up to 2367 MHz, 256 Kbyte L2 cache per core) + quad ARM Cortex-A510 (up to 1704 MHz, 128 Kbyte L2 cache per core) Harvard.. ›› |
Datasheet Attributes: |
Data Integrity |
Final |
Added |
2024-04-15 21:42 |