Generel Characteristics: |
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Designer | Apple |
Type: | A16 Bionic APL1010 / APL1W10 |
Codename: | T8120 |
Year Released: | 2022 |
Function | Application Processor |
Architecture: |
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Width of Machine Word | 64 bit |
Supported Instruction Set(s): | ARMv8.6-A (A32, A64) |
Type of processor core(s) | 2x Apple Everest + 4x Apple Sawtooth cores |
Number of processor core(s): | hexa-core |
Buses: |
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Memory Interface(s): | LPDDR4x SDRAM , LPDDR5 SDRAM |
Max. Clock Frequency of Memory IF | 3200 MHz |
Data Bus Width | 64 bit |
Number of data bus channels: | 2 ch |
Max. Data Rate | 102.4 Gbyte/s |
Non-volatile Memory Interface | moviNAND , NAND Flash Interface , SATA , SATA II , UFS 3.1 , UFS 3.1 2-lane |
Clock Frequencies: |
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Recommended Maximum Clock Frequency: | 3460 MHz max. |
Cache Memories: |
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Total L2 Cache | 20480 Kbyte L2 |
Total L3 Cache: | 24576 Kbyte L3 |
Technology and Packaging: |
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Feature Size | 5 nm |
Semiconductor Technology: | CMOS |
Number of Transistors Integrated: | 16000000000 |
Fab | TSMC |
Graphical Subsystem: |
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Embedded GPU | Apple A16 GPU |
Number of GPU cores: | 5-core GPU |
Cellular Communication: |
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Supported Cellular Data Links | No |
Additional Information: |
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Special Features: 2x high-performance Apple Everest 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3.46 GHz, 8 MiB L2 cache per core) + 4x high-efficiency Apple Sawtooth 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 2.02 GHz, 1 MiB L2.. ›› |
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Datasheet Attributes: |
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Data Integrity | Preliminary |
Added | 2022-09-10 15:55 |
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