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|
| Designer |
Apple |
| Type: | A13 Bionic APL1W85 T8030 |
| Codename: | Cebu |
| Year Released: | 2019 |
| Function |
Multi-core Application Processor |
|
|
| Width of Machine Word |
64 bit |
| Supported Instruction Set(s): | ARMv8.4-A (A32, A64) |
| Type of processor core(s) |
2x Apple Lightning + 4x Apple Thunder cores |
| Number of processor core(s): | hexa-core |
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|
| Memory Interface(s): | LPDDR4x SDRAM |
| Max. Clock Frequency of Memory IF |
2133 MHz |
| Data Bus Width |
16 bit |
| Number of data bus channels: | 4 ch |
| Max. Data Rate |
34.13 Gbyte/s |
| Non-volatile Memory Interface |
eMMC 5.1 |
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|
| Recommended Maximum Clock Frequency: | 2660 MHz max. |
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|
| L1 Instruction Cache per Core |
128 Kbyte I-Cache |
| L1 Data Cache per Core |
128 Kbyte D-Cache |
| Total L2 Cache |
4096 Kbyte L2 |
| Total L3 Cache: | 16384 Kbyte L3 |
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|
| Feature Size |
7 nm |
| Semiconductor Technology: |
FinFET |
| Number of Transistors Integrated: | 8500000000 |
| Fab |
TSMC |
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|
| Embedded GPU |
Apple A13 GPU |
| Number of GPU cores: | 4-core GPU |
| GPU Clock: | 1230 MHz GPU |
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| Supported Cellular Data Links |
No |
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|
| Special Features: APL1085, 2x high-performance Apple Lightning 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 2660 MHz, 128 KB L1 data cache per core, 128 KB L1 instruction cache per core) + 4x high-efficiency Apple Thunder 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar.. ›› |
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| Data Integrity |
Preliminary |
| Added |
2019-09-12 12:14 |
| Tweet | |