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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component MediaTek
Type Helio P60 MT6771
Year Released 2018
FunctionMain function of the component  Multi-core Application Processor with Modem

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit
Supported Instruction Set(s) ARMv8 (A32, A64)
Type of processor core(s)Type and allocation of processor core(s) 4x ARM Cortex-A73 + 4x ARM Cortex-A53 MPcore
Number of processor core(s) octa-core

BusesBuses: 
Memory Interface(s):   LPDDR3 SDRAM , LPDDR4x SDRAM
Address Bus WidthMaximum selectable bit width of address bus of memory interface 32 bit
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 1800 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 16 bit
Number of data bus channels 2 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 14.4 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  eMMC 5.1Complies with embedded MMC 5.1 specification released in 2015 , UFS 2.1UFS revision 2.1 (released in 2016) defines single-lane 600 MB/s or dual-lane 1.2 GB/s NAND flash EEPROM interface


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 2000 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 64 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 64 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 1024 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 12 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
FabPlant which fabricates the semiconductor component TSMC

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). ARM Mali-G72 GPU
Number of GPU cores 3-core GPU
GPU Clock 800 MHz GPU

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  CSDCircuit Switched Data (CSD) is the original data link protocol of GSM. Up to 9600bit/s download speed , GPRSGeneral Packet Radio Service , EDGEEnhanced Data Rates for GSM Evolution also known as Enhanced GPRS (EGPRS) , UMTSUniversal Mobile Telecommunications System. UMTS Release '99 data link layer, W-CDMA grants up to 384 kbit/s pocket-switched download speed. , HSUPAHigh-Speed Uplink Packet Access is a 3.5G UMTS uplink protocol. , HSUPA 1.4 , HSUPA 2.0 , HSUPA 5.8 , HSUPA 11.5 , HSDPAHigh-Speed Downlink Packet Access is a 3.5G UMTS downlink protocol. , HSDPA 1.8 , HSDPA 3.6 , HSDPA 7.2 , HSDPA 10.2 , HSDPA 14.4 , HSPA+ 21.1 , HSPA+ 42.2Single-carrier HSPA+ 42.2 Mbps , DC-HSDPA 42.2Dual-carrier HSPA+ 42.2 Mbps , CDMA2000 1x , CDMA2000 1xEV-DO , CDMA2000 1xEV-DO Rev A , TD-SCDMATime Division Synchronous Code Division Multiple Access is the implementation of UMTS  (3G) cellular network in China. , LTELTE (Long Term Evolution) or the E-UTRAN (Evolved Universal Terrestrial Access Network), introduced in 3GPP R8, is the 4G access part of the Evolved Packet System (EPS). , LTE 100/50LTE 100.8 Mbps / 50.4 Mbps (Cat. 3) , LTE 150/50LTE 151.2 Mbps / 50.4 Mbps (Cat. 4) , LTE 300/50More exact values: LTE 301.5 Mbps / 50.4 Mbps (Cat. 6) , LTE 300/100More exact values: LTE 301.5 Mbps / 100.8 Mbps (Cat. 7) , LTE 400/150LTE Category 13: 391.7 Mbps downlink, 150.8 Mbps uplink (rel. 12) data links

Additional InformationAdditional Information: 
Special Features
4x ARM Cortex-A73 (up to 2 GHz) + 4x ARM Cortex-A53 (up to 1989 MHz) Harvard Superscalar processor core, HMP, 32 bit 933 MHz LP-DDR3 / 2x16 bit 1800 MHz LP-DDR4x memory interface, integrated GSM / GPRS / UMTS /.. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2018-03-13 16:41
 
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