 Generel Characteristics:
|
Designer |
Samsung |
| Type: |
Exynos 9 Octa 9810 S5E9810 |
| Year Released: |
2018 |
| Function |
Multi-core Application Processor with Modem |
 Architecture:
|
| Width of Machine Word |
64 bit |
| Supported Instruction Set(s): |
ARMv8-A (A32, A64) |
| Type of processor core(s) |
4x Samsung Exynos M3 + 4x ARM Cortex-A55 MPcore |
| Number of processor core(s): |
octa-core |
 Buses:
|
| Memory Interface(s): |
LPDDR4x SDRAM |
| Max. Clock Frequency of Memory IF |
1794 MHz |
| Data Bus Width |
16 bit |
| Number of data bus channels: |
4 ch |
| Max. Data Rate |
28.7 Gbyte/s |
| Non-volatile Memory Interface |
NAND Flash Interface
, SATA
, UFS 2.1 |
 Clock Frequencies:
|
| Recommended Maximum Clock Frequency: |
2704 MHz max. |
 Cache Memories:
|
| Total L2 Cache |
2560 Kbyte L2 |
| Total L3 Cache: |
4096 Kbyte L3 |
 Technology and Packaging:
|
| Feature Size |
10 nm |
| Semiconductor Technology: |
CMOS |
| Fab |
Samsung |
 Graphical Subsystem:
|
| Embedded GPU |
ARM Mali-G72 GPU |
| Number of GPU cores: |
18-core GPU |
| GPU Clock: |
572 MHz GPU |
 Cellular Communication:
|
| Supported Cellular Data Links |
CSD
, GPRS
, EDGE
, EDGE MSC32
, UMTS
, HSUPA 5.8
, HSDPA
, HSPA+ 21.1
, DC-HSDPA 42.2
, cdmaOne
, CDMA2000 1x
, CDMA2000 1xEV-DO
, CDMA2000 1xEV-DO Rev A
, CDMA2000 1xEV-DO Rev B
, TD-SCDMA
, LTE
, LTE 100/50
, LTE 150/50
, LTE 300/50
, LTE 300/75
, LTE 300/100
, LTE 400/150
, LTE 450/50
, LTE 450/100
, LTE 600/50
, LTE 600/100
, LTE 1000/100
, LTE 1200/200 data links |
 Additional Information:
|
Special Features:
Quad Samsung Exynos M3 Harvard Superscalar processor cores (up to 2.7 GHz, 512 Kbyte L2 cache per core) + Quad ARM Cortex-A55 (up to 1.95 GHz, 512 Kbyte total L3 cache) Harvard Superscalar processor cores, HMP, ARM big.LITTLE architecture,.. ›› |
 Datasheet Attributes:
|
| Data Integrity |
Preliminary |
| Added |
2017-11-13 14:56 |
All details | 
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