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Designer![]() |
Apple |
Type: | A10X Fusion APL1071 / APL1W71 |
Codename: | T8011 |
Year Released: | 2017 |
Function![]() |
SoC |
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Width of Machine Word![]() |
64 bit |
Supported Instruction Set(s): | ARMv8.1-A (A32, A64) |
Type of processor core(s)![]() |
3x Apple Hurricane + 3x Zephyr cores |
Number of processor core(s): | quad-core |
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Memory Interface(s): | LPDDR4 SDRAM |
Max. Clock Frequency of Memory IF![]() |
1600 MHz |
Data Bus Width![]() |
64 bit |
Number of data bus channels: | 2 ch |
Max. Data Rate![]() |
51.2 Gbyte/s |
Non-volatile Memory Interface![]() |
eMMC 5.1![]() ![]() ![]() |
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Recommended Maximum Clock Frequency: | 2380 MHz max. |
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L1 Instruction Cache per Core![]() |
64 Kbyte I-Cache |
L1 Data Cache per Core![]() |
64 Kbyte D-Cache |
Total L2 Cache![]() |
3072 Kbyte L2 |
Total L3 Cache: | 8192 Kbyte L3 |
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Feature Size![]() |
10 nm |
Semiconductor Technology: |
FinFET![]() |
Number of Transistors Integrated: | 4000000000 |
Fab![]() |
TSMC |
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Embedded GPU![]() |
IMG PowerVR GT7600 Plus GPU |
Number of GPU cores: | 12-core GPU |
GPU Clock: | 1000 MHz GPU |
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Supported Cellular Data Links![]() |
No |
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Special Features: 3x high-performance 2.38 GHz Apple Hurricane 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (64 Kbyte L1i cache per core + 64 Kbyte L1d cache per core) + 3x high-efficiency 1.3 GHz Apple Zephyr 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores.. ›› |
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Data Integrity![]() |
Preliminary |
Added![]() |
2017-06-06 18:48 |
Tweet | |