 Generel Characteristics:
|
Designer |
HiSilicon |
| Type: |
Honor KIRIN955 |
| Year Released: |
2016 |
| Function |
Multi-core Application Processor with Modem |
 Architecture:
|
| Width of Machine Word |
64 bit |
| Supported Instruction Set(s): |
ARMv8-A (A32, A64) |
| Type of processor core(s) |
4x ARM Cortex-A72 MPcore + 4x ARM Cortex-A53 MPcore |
| Number of processor core(s): |
octa-core |
 Buses:
|
| Memory Interface(s): |
LPDDR3 SDRAM
, LPDDR4 SDRAM |
| Max. Clock Frequency of Memory IF |
1333 MHz |
| Data Bus Width |
32 bit |
| Number of data bus channels: |
2 ch |
| Max. Data Rate |
21.33 Gbyte/s |
| Non-volatile Memory Interface |
eMMC 5.1
, UFS 2.0 |
 Clock Frequencies:
|
| Recommended Maximum Clock Frequency: |
2520 MHz max. |
 Cache Memories:
|
| L1 Instruction Cache per Core |
48 Kbyte I-Cache |
| L1 Data Cache per Core |
32 Kbyte D-Cache |
 Technology and Packaging:
|
| Feature Size |
16 nm |
| Semiconductor Technology: |
CMOS |
| Fab |
TSMC |
 Graphical Subsystem:
|
| Embedded GPU |
ARM Mali-T880 GPU |
| Number of GPU cores: |
4-core GPU |
| GPU Clock: |
900 MHz GPU |
 Cellular Communication:
|
| Supported Cellular Data Links |
CSD
, GPRS
, GPRS MSC33
, EDGE
, UMTS
, HSUPA
, HSUPA 5.8
, HSDPA
, HSPA+ 42.2
, DC-HSDPA 42.2
, TD-SCDMA
, TD-HSDPA
, LTE
, LTE 100/50
, LTE 150/50
, LTE 300/50 data links |
 Additional Information:
|
Special Features:
quad ARM Cortex-A72 (up to 2.52 GHz) + quad ARM Cortex-A53 (up to 1.81 GHz) Harvard Superscalar processor cores, ARM big.LITTLE, HMP, SD 4.1 (UHS-II), GSM / GPRS Class 33 / EDGE / W-CDMA / HSPA+ 42.2 Mbps / HSUPA.. ›› |
 Datasheet Attributes:
|
| Data Integrity |
Preliminary |
| Added |
2016-04-07 07:16 |
All details | 
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