Generel Characteristics: |
Designer |
Freescale |
Type: |
i.MX535D VV1C |
Codename: |
MCIMX535DVV1C |
Year Released: |
2011 |
Function |
Application Processor |
Architecture: |
Width of Machine Word |
32 bit |
Supported Instruction Set(s): |
ARMv7 |
Pipeline Stages |
13 pipeline stages |
Type of processor core(s) |
ARM Cortex-A8 |
Number of processor core(s): |
single-core |
Buses: |
Memory Interface(s): |
DDR2 SDRAM
, LPDDR2 SDRAM
, DDR3 SDRAM |
Max. Clock Frequency of Memory IF |
400 MHz |
Data Bus Width |
32 bit |
Number of data bus channels: |
1 ch |
Max. Data Rate |
3.2 Gbyte/s |
Non-volatile Memory Data Bus Width |
16 bit |
Non-volatile Memory Interface |
NOR Flash Interface |
Clock Frequencies: |
Recommended Minimum Clock Frequency: |
800 MHz min. |
Recommended Maximum Clock Frequency: |
1000 MHz max. |
Cache Memories: |
L1 Instruction Cache per Core |
32 Kbyte I-Cache |
L1 Data Cache per Core |
32 Kbyte D-Cache |
Total L2 Cache |
256 Kbyte L2 |
Technology and Packaging: |
Semiconductor Technology: |
CMOS |
Fab |
Freescale |
Pins |
529 pins |
Graphical Subsystem: |
Embedded GPU |
N/A |
Cellular Communication: |
Supported Cellular Data Links |
No |
Additional Information: |
Special Features: 128KB shared SRAM, MMU, Smart DMA, ARM NEON SIMD engine, ARM TrustZone, 64-bit AMBA AXI v1.0 bus, 32-bit AMBA AHB 2.0 bus, vector floating point (VFP-Lite), 16/32-bit DDR2-800, LV-DDR2-800, DDR3-800, 32-bit LPDDR2 RAM interface, 8/16-bit NAND SLC/MLC Flash , 4/8/14/16-bit.. ›› |
Datasheet Attributes: |
Data Integrity |
Final |
Added |
2012-02-04 12:30 |