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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Samsung-Intrinsity
Type Apple A4 APL0398
Codename S5PC110A01
Year Released 2010
FunctionMain function of the component  System-On-a-Chip

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv7
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 13 pipeline stages
Number of processor core(s) 1
Type of processor core(s)Type and allocation of processor core(s) Samsung Hummingbird

BusesBuses: 
Memory Interface(s):   mobile (LP) DDR SDRAM , mobile (LP) DDR2 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 100 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 0.8 Gbyte/s
Non-volatile Memory Data Bus WidthMaximum selectable bit width of secondary data (non-volatile storage) bus of memory interface 32 bit
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  Yes
DMA ChannelsDMA (Direct Memory Access) allows direct data transfer between operative memory (RAM) and peripherals (hard disk, non-volatile storage, etc.) bypassing processor core. Multiple DMA channels allows parallel DMA operations. 32 ch


Clock FrequenciesClock Frequencies: 
Recommended Minimum Clock Frequency 800 MHz min.
Recommended Maximum Clock Frequency 1000 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 32 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 32 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 640 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 45 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
FabPlant which fabricates the semiconductor component Samsung

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). IMG PowerVR SGX535 GPU
Number of GPU cores 1-core GPU
GPU Clock 200 MHz GPU

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Communication InterfacesCommunication Interfaces: 
Supported USB Specification:   No
Bluetooth supportThis field specifies the supported BT version  No
Wireless LAN supportThis field enumerates the supported Wi-Fi protocols  No
Supported Audio/Video Interface:   No

Satellite NavigationSatellite Navigation: 
Supported GPS protocol(s):   No

Additional InformationAdditional Information: 
Special Features
Fully ARM Cortex-A8 compatible, 64/32-bit Multi-layer AHB/AXI bus, ARM TrustZone, 2x 128MB integrated DDR SDRAM, NEON SIMD engine, OneDRAM, vector floating point coprocessor (VPU), 32-channel DMA, 1080p full HD codec engine, HDMI 1.3 interface, OpenGL ES 2.0

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2010-02-02 22:25
 
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