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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Samsung-Intrinsity
Type Hummingbird Core
Year Released 2009
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv7
Type of processor core(s)Type and allocation of processor core(s) Samsung Hummingbird
Number of processor core(s) single-core

BusesBuses: 
Memory Interface(s):   Yes
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 64 bit
Number of data bus channels 1 ch
Non-volatile Memory Data Bus WidthMaximum selectable bit width of secondary data (non-volatile storage) bus of memory interface 32 bit
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  No


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 1000 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 32 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 32 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 128 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 45 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
FabPlant which fabricates the semiconductor component Samsung

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Additional InformationAdditional Information: 
Special Features
Fully ARM Cortex-A8 compatible, 64/32-bit Multi-layer AHB/AXI bus, ARM TrustZone, ARM NEON SIMD engine, vector floating point coprocessor (VPU), customisable L2 cache size

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Incomplete
AddedThe exact time of the datasheet addition 2009-07-28 21:57
 
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