|
|
Designer |
Centrality |
| Type: | Titan GPS V5 |
| Year Released: | 2007 |
| Function |
SoC |
|
|
| Width of Machine Word |
32 bit |
| Supported Instruction Set(s): | ARMv6 |
| Pipeline Stages |
8 pipeline stages |
| Type of processor core(s) |
ARM1136EJ-S |
| Number of processor core(s): | single-core |
|
|
| Memory Interface(s): | SDRAM , DDR SDRAM |
| Data Bus Width |
32 bit |
| Number of data bus channels: | 1 ch |
| Non-volatile Memory Data Bus Width |
32 bit |
| Non-volatile Memory Interface |
Yes |
|
|
| Recommended Minimum Clock Frequency: | 600 MHz min. |
| Recommended Maximum Clock Frequency: | 650 MHz max. |
|
|
| L1 Instruction Cache per Core |
16 Kbyte I-Cache |
| L1 Data Cache per Core |
16 Kbyte D-Cache |
| Total L2 Cache |
128 Kbyte L2 |
|
|
| Semiconductor Technology: |
CMOS |
| Pins |
477 pins |
|
|
| Embedded GPU |
N/A |
|
|
| Supported Cellular Data Links |
No |
|
|
| Special Features: MMU, AMBA 2.0 AHB, ARM Jazelle, VFPU, integrated 40+ channels Centrality GPS V5 DSP |
|
|
|
| Data Integrity |
Final |
| Added |
2007-09-08 19:02 |
| Tweet | |
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