 Generel Characteristics:
|
Designer |
Apple |
| Type: |
A16 Bionic Lite APL1010 / APL1W10 |
| Year Released: |
2025 |
| Function |
Multi-core Application Processor |
 Architecture:
|
| Width of Machine Word |
64 bit |
| Supported Instruction Set(s): |
ARMv8.6-A (A32, A64) |
| Type of processor core(s) |
2x Apple Everest + 3x Apple Sawtooth cores |
| Number of processor core(s): |
penta-core |
 Buses:
|
| Memory Interface(s): |
LPDDR4x SDRAM
, LPDDR5 SDRAM |
| Max. Clock Frequency of Memory IF |
3200 MHz |
| Data Bus Width |
16 bit |
| Number of data bus channels: |
4 ch |
| Max. Data Rate |
51.2 Gbyte/s |
| Non-volatile Memory Interface |
moviNAND
, NAND Flash Interface
, SATA
, SATA II
, UFS 3.1
, UFS 3.1 2-lane |
 Clock Frequencies:
|
| Recommended Maximum Clock Frequency: |
3460 MHz max. |
 Cache Memories:
|
| L1 Instruction Cache per Core |
192 Kbyte I-Cache |
| L1 Data Cache per Core |
128 Kbyte D-Cache |
| Total L2 Cache |
19456 Kbyte L2 |
 Technology and Packaging:
|
| Feature Size |
4 nm |
| Semiconductor Technology: |
FinFET |
| Fab |
TSMC |
 Graphical Subsystem:
|
| Embedded GPU |
Apple G15P GPU |
| Number of GPU cores: |
4-core GPU |
| GPU Clock: |
1338 MHz GPU |
 Cellular Communication:
|
| Supported Cellular Data Links |
No |
 Additional Information:
|
Special Features:
2x high-performance Apple Everest 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3.46 GHz, 192 KB L1 data cache per core, 128 KB L1 instruction cache per core, 8 MiB L2 cache per core) + 3x high-efficiency Apple Sawtooth.. ›› |
 Datasheet Attributes:
|
| Data Integrity |
Preliminary |
| Added |
2025-05-29 20:59 |
All details | 
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