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Ingenic M200

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Generel Characteristics: 
DesignerCompany which designed the semiconductor component Ingenic
Type M200
Year Released 2015
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) MIPS32
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 9 pipeline stages
Type of processor core(s)Type and allocation of processor core(s) 1x MIPS XBurst-HP + 1x MIPS XBurst-LP
Number of processor core(s) dual-core

BusesBuses: 
Memory Interface(s):   LPDDR SDRAM, DDR2 SDRAM, LPDDR2 SDRAM, DDR3 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 667 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 5.34 Gbyte/s
Secondary Data Bus WidthMaximum selectable bit width of secondary data (non-volatile storage) bus of memory interface 64 bit


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 1200 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 32 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 32 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 512 Kbyte L2

Technology and Packaging: 
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
PinsNumber of pins on the package 270 pins

Additional Features: 
Number of GPU cores 1-core GPU
Special Features 1x XBurst-HP (1.2GHz) + 1x XBurst-LP (300 MHz)..

Datasheet Attributes: 
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2018-02-09 15:37
 
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