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DEC StrongARM SA-1100 datasheet

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Generel Characteristics: 
DesignerCompany which designed the semiconductor component DEC
Type StrongARM SA-1100
Year Released 1997
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv4
Number of processor core(s) 1
Type of processor core(s)Type and allocation of processor core(s) ARM SA-1

BusesBuses: 
Memory Interface(s):   SDRAM
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch

Clock FrequenciesClock Frequencies: 
Internal Systembus Clock 66 MHz
Recommended Maximum Clock Frequency 190 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 16 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 8 Kbyte D-Cache

Technology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 350 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
Number of Transistors Integrated 2500000
PinsNumber of pins on the package 208 pins

Additional Features: 
Special Features embedded flash ROM, FPM / EDO DRAM / SDRAM / SRAM interface, flash ROM / ROM interface, MMU, Write buffer, Read buffer, LCD controller, serial I/O, PCMCIA controller


Datasheet Attributes: 
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2016-08-17 21:53
 
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