PhoneDB - infinitely detailed




FacebookGoogle PlusRSS FeedTwitter

Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Qualcomm
Type Snapdragon 800 APQ8074 v1
Codename Snapdragon S4 Prime
Year Released 2013
FunctionMain function of the component  Multi-core Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv7
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 11 pipeline stages
Type of processor core(s)Type and allocation of processor core(s) 4x Qualcomm Krait 400
Number of processor core(s) quad-core

BusesBuses: 
Memory Interface(s):   LPDDR3 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 800 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 2 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 12.8 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  eMMC 4.5 , eMMC 5.0 , SATASATA revision 1.0 (2003) offering 1.5 Gbit/s data rate , SATA IISerial AT Attachment revision 2.0 (released in 2004) or 2.x offering 3 Gbit/s data rate


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 2265 MHz max.

Cache MemoriesCache Memories: 
L0 Instruction Cache per CoreCapacity of level 0 instruction cache per processor core 4 Kbyte L0 I-Cache
L0 Data Cache per CoreCapacity of level 0 data cache per processor core 4 Kbyte L0 D-Cache
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 16 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 16 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 2048 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 28 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
FabPlant which fabricates the semiconductor component TSMC

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). Qualcomm Adreno 330 GPU
Dedicated Graphics MemoryDedicated operative memory (video RAM, VRAM) 1 MiB

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Additional InformationAdditional Information: 
Special Features
4x Qualcomm Krait 400 Harvard Superscalar processor core, 600 MHz Hexagon QDSP6V5A, Adreno 330 GPU, OpenCL support, 55 MP camera support, Stereoscopic 3D Kit, 2160p video encode/decode, gpsOneGen 8B with GLONASS, USB 3.0, OpenGL ES 3.0, OpenCL 1.1, OpenVG 1.1,.. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2013-03-02 13:26
 
You are here: Processor Specs \ Qualcomm Snapdragon 800 APQ8074 v1 (Snapdragon S4 Prime)