ZiiLABS ZMS-08 datasheet

Generel Characteristics:
Designer	ZiiLABS
Type:	ZMS-08
Year Released:	2009
Function	Application Processor
Collapse datasheet \| Add to compare Architecture:
Width of Machine Word	32 bit
Supported Instruction Set(s):	ARMv7
Pipeline Stages	13 pipeline stages
Number of processor core(s):	1
Type of processor core(s)	ARM Cortex-A8
Buses:
Memory Interface(s):	SDRAM , DDR SDRAM , mobile (LP) DDR SDRAM , DDR2 SDRAM
Data Bus Width	64 bit
Number of data bus channels:	1 ch
Non-volatile Memory Data Bus Width	32 bit
Non-volatile Memory Interface	NAND Flash Interface , NOR Flash Interface
Clock Frequencies:
Recommended Maximum Clock Frequency:	1000 MHz max.
Cache Memories:
L1 Instruction Cache per Core	32 Kbyte I-Cache
L1 Data Cache per Core	32 Kbyte D-Cache
Total L2 Cache	256 Kbyte L2
Technology and Packaging:
Semiconductor Technology:	CMOS
Pins	434 pins
Graphical Subsystem:
Embedded GPU	N/A
Collapse datasheet Cellular Communication:
Supported Cellular Data Links	No
Communication Interfaces:
Supported USB Specification:	No
Bluetooth support	No
Wireless LAN support	No
Supported Audio/Video Interface:	No
Satellite Navigation:
Supported GPS protocol(s):	No
Additional Information:
Special Features: SIMD Media Processing Array (64 Precessing elements), Xtreme Fidelity X-Fi Audio Processing, Dual USB 2.0, Dual USB 2.0 OTG controllers with on-chip PHY and ULPI interfaces, Three SD/SDIO/MMC/CE-ATA controllers, Dual high fidelity digital audio ports, I2S/PCM, I2C, 5 UARTs, 113 GPIOs, Hi-Speed Serial Input, Flexible General Interface Bus, PLLs, OpenGL ES 1.1 and 2.0 3D graphics, Four Independent, Bi-directional HD Capable Video Ports, Connect to LCDs up to 24-bit, Connect to Multiple High Resolution Cameras, Integrated Analog HD TV encoder, Intergrated HDMI transmitter
Datasheet Attributes:
Related Page:	URL
Data Integrity	Final
Added	2010-07-14 22:45